TLP152
Photocouplers
GaAℓAs Infrared LED & Photo IC
TLP152
1. Applications
•
•
•
•
Plasma Display Panels (PDPs)
Industrial Inverters
MOSFET Gate Drivers
IGBT Gate Drivers
2. General
The TLP152 is a photocoupler in an SO6 package that consists of a GaAℓAs infrared light-emitting diode (LED)
optically coupled to an integrated high-gain, high-speed photodetector IC chip. The photodetector IC chip has an
internal shield to provide a high common-mode transient immunity of
±20
kV/µs and thus superior noise immunity
between the input and output pins. The TLP152 has a totem-pole output that can both sink and source current.
It is suitable for directly driving a small IGBT or power MOSFET.
3. Features
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Buffer logic type (totem pole output)
Output peak current:
±2.5
A (max)
Operating temperature: -40 to 100
Supply current: 3.0 mA (max)
Supply voltage: 10 to 30 V
Threshold input current: 7.5 mA (max)
Propagation delay time: t
pHL
= 190 ns (max), t
pLH
= 170 ns (max)
Common-mode transient immunity:
±20
kV/µs (min)
Isolation voltage: 3750 Vrms (min)
UL-approved: UL1577, File No.E67349
cUL-approved: CSA Component Acceptance Service No.5A File No.E67349
VDE-approved: EN60747-5-5, EN60065 or EN60950-1 (Note 1)
: EN62368-1 (Pending) (Note 1)
CQC-approved: GB4943.1, GB8898 Thailand Factory
(10) Safety standards
Note 1: When a VDE approved type is needed, please designate the Option (V4)
(V4).
Start of commercial production
©2016-2017
Toshiba Electronic Devices & Storage Corporation
1
2012-06
2017-12-19
Rev.6.0
TLP152
4. Packaging and Pin Assignment
1: Anode
3: Cathode
4: GND
5: V
O
6: V
CC
11-4L1S
5. Internal Circuit (Note)
Note:
A 0.1-µF bypass capacitor must be connected between pin 6 and pin 4.
6. Principle of Operation
6.1. Truth Table
Input
H
L
LED
ON
OFF
M1
ON
OFF
M2
OFF
ON
Output
H
L
6.2. Mechanical Parameters
Characteristics
Creepage distances
Clearance distances
Internal isolation thickness
Size
5.0 (min)
5.0 (min)
0.4 (min)
Unit
mm
©2016-2017
Toshiba Electronic Devices & Storage Corporation
2
2017-12-19
Rev.6.0
TLP152
7. Absolute Maximum Ratings (Note) (Unless otherwise specified, T
a
= 25
)
Characteristics
LED
Input forward current
Peak transient input forward
current
Input reverse voltage
Input power dissipation
Detector Peak high-level output current
Peak low-level output current
Output voltage
Supply voltage
Output power dissipation
Output power dissipation
derating
Common Operating temperature
Storage temperature
Lead soldering temperature
Isolation voltage
(10 s)
(AC, 60 s, R.H.
≤
60 %)
(T
a
≥
85
)
(T
a
= -40 to 100
)
(T
a
= -40 to 100
)
Symbol
I
F
I
FPT
V
R
P
D
I
OPH
I
OPL
V
O
V
CC
P
O
∆P
O
/∆T
a
T
opr
T
stg
T
sol
BV
S
(Note 3)
(Note 4)
(Note 2)
(Note 2)
(Note 1)
Note
Rating
20
1
5
40
-2.5
+2.5
35
35
260
-2.0
-40 to 100
-55 to 125
260
3750
Vrms
mW
mW/
V
Unit
mA
A
V
mW
A
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: Pulse width (PW)
≤
1
µs,
300 pps
Note 2: Exponential waveform. Pulse width
≤
0.2
µs,
f
≤
15 kHz, V
CC
= 20 V, T
a
= -40 to 100
Exponential waveform. Pulse width
≤
0.08
µs,
f
≤
25 kHz, V
CC
= 15 V, T
a
= -40 to 100
Note 3:
≥
2 mm below seating plane.
Note 4: This device is considered as a two-terminal device: Pins 1 and 3 are shorted together, and pins 4, 5 and 6 are
shorted together.
Note:
8. Recommended Operating Conditions (Note)
Characteristics
Input on-state current
Input off-state voltage
Peak high-level output current
Peak low-level output current
Operating frequency
Symbol
I
F(ON)
V
F(OFF)
I
OPH
I
OPL
f
(Note 2)
Note
(Note 1)
Min
10
0
Typ.
Max
15
0.8
-2.0
+2.0
250
kHz
Unit
mA
V
A
The recommended operating conditions are given as a design guide necessary to obtain the intended
performance of the device. Each parameter is an independent value. When creating a system design using
this device, the electrical characteristics specified in this data sheet should also be considered.
Note: A ceramic capacitor (0.1
µF)
should be connected between pin 6 and pin 4 to stabilize the operation of a high-
gain linear amplifier. Otherwise, this photocoupler may not switch properly. The bypass capacitor should be
placed within 1 cm of each pin.
Note 1: The rise and fall times of the input on-current should be less than 0.5
µs.
Note 2: Exponential waveform. I
OPH
≥
-0.65 A (≤ 80 ns), I
OPL
≤
0.65 A (≤ 80 ns), T
a
= 100
,
V
CC
= 20 V
Note:
©2016-2017
Toshiba Electronic Devices & Storage Corporation
3
2017-12-19
Rev.6.0
TLP152
9. Electrical Characteristics (Note) (Unless otherwise specified, T
a
= -40 to 100
)
Characteristics
Input forward voltage
Input forward voltage
temperature coefficient
Input reverse current
Input capacitance
Peak high-level output current
Symbol
V
F
∆V
F
/∆T
a
I
R
C
t
I
OPH
(Note 1)
Note
Test
Circuit
Fig.
12.1.1
Test Condition
I
F
= 10 mA, T
a
= 25
I
F
= 10 mA
V
R
= 5 V, T
a
= 25
V = 0 V, f = 1 MHz, T
a
= 25
I
F
= 10 mA, V
CC
= 15 V,
V
6-5
= 4 V
I
F
= 10 mA, V
CC
= 15 V,
V
6-5
= 10 V
Peak low-level output current
I
OPL
(Note 1)
Fig.
12.1.2
I
F
= 0 mA, V
CC
= 15 V,
V
5-4
= 2 V
I
F
= 0 mA, V
CC
= 15 V,
V
5-4
= 10 V
High-level output voltage
Low-level output voltage
High-level supply current
Low-level supply current
Threshold input current (L/H)
Threshold input voltage (H/L)
Supply voltage
UVLO threshold voltage
V
OH
V
OL
I
CCH
I
CCL
I
FLH
V
FHL
V
CC
V
UVLO
+
V
UVLO
-
UVLO hysteresis
UVLO
HYS
Fig.
12.1.3
Fig.
12.1.4
Fig.
12.1.5
Fig.
12.1.6
I
F
= 10 mA, V
CC
= 10 V,
I
O
= -100 mA
V
F
= 0.8 V, V
CC
= 10 V,
I
O
= 100 mA
I
F
= 10 mA, V
CC
= 10 to 30 V,
V
O
= Open
I
F
= 0 mA, V
CC
= 10 to 30 V,
V
O
= Open
V
CC
= 15 V, V
O
> 1 V
V
CC
= 15 V, V
O
< 1 V
I
F
= 5 mA, V
O
> 2.5 V
I
F
= 5 mA, V
O
< 2.5 V
I
F
= 5 mA, V
O
> 2.5 V
Min
1.40
1.0
2.0
6.0
0.8
10
7.8
7.5
Typ.
1.57
-1.8
45
-2.2
-3.4
2.4
3.5
8.5
0.1
1.9
1.8
1.5
1.47
8.7
8.4
0.3
Max
1.80
10
-1.0
-2.0
1.0
3.0
3.0
7.5
30
9.7
9.4
V
mA
V
Unit
V
mV/
µA
pF
A
Note:
Note:
All typical values are at T
a
= 25
.
This device is designed for low power consumption, making it more sensitive to ESD than its predecessors.
Extra care should be taken in the design of circuitry and pc board implementation to avoid ESD problems.
Note 1: I
O
application time
≤
50
µs,
single pulse.
10. Isolation Characteristics (Unless otherwise specified, T
a
= 25
)
Characteristics
Total capacitance (input to output)
Isolation resistance
Isolation voltage
Symbol
C
S
R
S
BV
S
Note
Test Conditions
Min
1
×
10
12
3750
Typ.
0.35
10
14
10000
10000
Max
Vdc
Unit
pF
Ω
Vrms
(Note 1) V
S
= 0 V, f = 1 MHz
(Note 1) V
S
= 500 V, R.H.
≤
60 %
(Note 1) AC, 60 s
AC, 1 s in oil
DC, 60 s in oil
Note 1: This device is considered as a two-terminal device: Pins 1 and 3 are shorted together, and pins 4, 5 and 6 are
shorted together.
©2016-2017
Toshiba Electronic Devices & Storage Corporation
4
2017-12-19
Rev.6.0
TLP152
11. Switching Characteristics (Note) (Unless otherwise specified, T
a
= -40 to 100
)
Characteristics
Propagation delay time
(L/H)
Propagation delay time
(H/L)
Propagation delay time
(L/H)
Propagation delay time
(H/L)
Propagation delay skew
(device to device)
Pulse width distortion
Rise time
Fall time
Common-mode transient
immunity at output high
Common-mode transient
immunity at output low
Symbol
t
pLH
Note
(Note 1)
Test
Circuit
Fig.
12.1.7
Test Condition
I
F
= 0
→
10 mA, V
CC
= 30 V,
R
g
= 20
Ω,
C
g
= 10 nF,
T
a
= 25
I
F
= 10
→
0 mA, V
CC
= 30 V,
R
g
= 20
Ω,
C
g
= 10 nF,
T
a
= 25
I
F
= 0
→
10 mA, V
CC
= 30 V,
R
g
= 20
Ω,
C
g
= 10 nF
I
F
= 10
→
0 mA, V
CC
= 30 V,
R
g
= 20
Ω,
C
g
= 10 nF
I
F
= 0
←→
10 mA, V
CC
= 30 V,
R
g
= 20
Ω,
C
g
= 10 nF
I
F
= 0
←→
10 mA, V
CC
= 30 V,
R
g
= 20
Ω,
C
g
= 10 nF
I
F
= 0
→
10 mA, V
CC
= 30 V,
R
g
= 20
Ω,
C
g
= 10 nF
I
F
= 10
→
0 mA, V
CC
= 30 V,
R
g
= 20
Ω,
C
g
= 10 nF
Fig.
12.1.8
V
CM
= 1000 V
p-p
, I
F
= 10 mA,
V
CC
= 30 V, T
a
= 25,
V
O(min)
= 26 V
V
CM
= 1000 V
p-p
, I
F
= 0 mA,
V
CC
= 30 V, T
a
= 25,
V
O(max)
= 1 V
Min
60
Typ.
95
Max
145
Unit
ns
t
pHL
(Note 1)
60
110
165
t
pLH
t
pHL
t
psk
(Note 1)
(Note 1)
(Note 1)
(Note 4)
50
50
-85
±20
95
110
15
18
22
170
190
85
50
kV/µs
|t
pHL
-t
pLH
| (Note 1)
t
r
t
f
CM
H
(Note 1)
(Note 1)
(Note 2)
CM
L
(Note 3)
±20
Note: All typical values are at T
a
= 25
.
Note 1: Input signal (f = 125 kHz, duty = 50 %, t
r
= t
f
= 5 ns or less).
CL is approximately 15 pF which includes probe and stray wiring capacitance.
Note 2: CM
H
is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in
the logic high state (V
O
> 26 V).
Note 3: CM
L
is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage
in the logic low state (V
O
< 1 V).
Note 4: The propagation delay skew, t
psk
, is equal to the magnitude of the worst-case difference in t
pHL
and/or t
pLH
that will be seen between units at the same given conditions (supply voltage, input current, temperature, etc).
©2016-2017
Toshiba Electronic Devices & Storage Corporation
5
2017-12-19
Rev.6.0
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