TC58NVG1S3HTA00
MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2 GBIT (256M
×
8 BIT) CMOS NAND E
2
PROM
DESCRIPTION
The TC58NVG1S3HTA00 is a single 3.3V 2Gbit (2,281,701,376 bits) NAND Electrically Erasable and
Programmable Read-Only Memory (NAND E
2
PROM) organized as (2048 + 128) bytes
×
64 pages
×
2048 blocks.
The device has two 2176-byte static registers which allow program and read data to be transferred between the
register and the memory cell array in 2176-byte increments. The Erase operation is implemented in a single block
unit (128 Kbytes + 8 Kbytes: 2176 bytes
×
64 pages).
The TC58NVG1S3HTA00 is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed, making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
•
Organization
Memory cell array
Register
Page size
Block size
x8
2176
×
128K
×
8
2176
×
8
2176 bytes
(128K
+
8K) bytes
•
Modes
Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy,
Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read
Mode control
Serial input/output
Command control
Number of valid blocks
Min 2008 blocks
Max 2048 blocks
•
•
•
Power supply
V
CC
=
2.7V to 3.6V
•
Access time
Cell array to register
Read Cycle Time
Program/Erase time
Auto Page Program
Auto Block Erase
Operating current
Read (25 ns cycle)
Program (avg.)
Erase (avg.)
Standby
Package
TSOP I 48-P-1220-0.50
25
µs
max
25 ns min (C
L
=50pF)
300
µs/page
typ.
2.5 ms/block typ.
30 mA max
30 mA max
30 mA max
50
µA
max
(Weight: 0.53 g typ.)
•
•
•
•
8 bit ECC for each 512Byte is required.
© 2012-2018 Toshiba Memory Corporation
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2018-12-14C
TC58NVG1S3HTA00
PIN ASSIGNMENT (TOP VIEW)
TC58NVG1S3HTA00
×8
NC
NC
NC
NC
NC
NC
--------
RY /
--------
BY
RE
--------
CE
NC
NC
V
CC
V
SS
NC
NC
CLE
ALE
--------
WE
--------
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
×8
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
NC
NC
V
CC
V
SS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
PIN NAMES
I/O1 to I/O8
--------
I/O port
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
Power supply
Ground
No Connection
CE
WE
--------
--------
RE
CLE
ALE
WP
RY / BY
V
CC
V
SS
NC
--------
--------
© 2012-2018 Toshiba Memory Corporation
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2018-12-14C
TC58NVG1S3HTA00
BLOCK DIAGRAM
V
CC
V
SS
Status register
I/O1
to
I/O8
I/O
Control circuit
Address register
Column buffer
Column decoder
Command register
Data register
Sense amp
--------
CLE
ALE
WE
--------
--------
Logic control
Control circuit
Row address decoder
CE
Row address buffer
decoder
Memory cell array
RE
WP
RY / BY
RY / BY
--------
--------
--------
HV generator
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
V
IN
V
I/O
P
D
T
STG
T
OPR
Power Supply Voltage
Input Voltage
Input / Output Voltage
Power Dissipation
Storage Temperature
Operating Temperature
RATING
VALUE
−0.6
to 4.6
−0.6
to 4.6
−0.6
to V
CC
+
0.3 (≤ 4.6 V)
0.3
−55
to 150
0 to 70
UNIT
V
V
V
W
°C
°C
Note: Avoid locations where the device may be exposed to water (wet, rain, dew condensation, etc.)
CAPACITANCE
*(Ta
=
25°C, f
=
1 MHz)
SYMBOL
C
IN
C
OUT
*
Input
Output
PARAMETER
CONDITION
V
IN
=
0 V
V
OUT
=
0 V
MIN
MAX
10
10
UNIT
pF
pF
This parameter is periodically sampled and is not tested for every device.
© 2012-2018 Toshiba Memory Corporation
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2018-12-14C
TC58NVG1S3HTA00
VALID BLOCKS
SYMBOL
N
VB
NOTE:
PARAMETER
Number of Valid Blocks
MIN
2008
TYP.
MAX
2048
UNIT
Blocks
The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime.
DC OPERATING CONDITIONS
SYMBOL
V
CC
Power Supply Voltage
PARAMETER
MIN
2.7
TYP.
MAX
3.6
UNIT
V
V
IH
High Level Input Voltage
V
CC
x 0.8
V
CC
+
0.3
V
V
IL
*
Low Level Input Voltage
−0.3*
V
CC
x 0.2
V
−2
V (pulse width lower than 20 ns)
DC CHARACTERISTICS
(Ta
=
0 to 70°C, V
CC
=
2.7 to 3.6V)
SYMBOL
I
IL
I
LO
I
CCO1
I
CCO2
I
CCO3
I
CCS
V
OH
V
OL
I
OL
--------
(RY / BY)
PARAMETER
Input Leakage Current
Output Leakage Current
Serial Read Current
Programming Current
Erasing Current
Standby Current
High Level Output Voltage
Low Level Output Voltage
Output Current of RY / BY pin
--------
--------
CONDITION
V
IN
=
0 V to V
CC
V
OUT
=
0 V to V
CC
--------
MIN
V
CC
– 0.2
TYP.
4
MAX
±10
±10
30
30
30
50
0.2
UNIT
µA
µA
mA
mA
mA
µA
V
V
mA
CE
=
V
IL
, I
OUT
=
0 mA, t
RC
=
25 ns
CE
=
V
CC
−
0.2 V, WP
=
0 V/V
CC
--------
I
OH
= −0.1
mA
I
OL
=
0.1 mA
V
OL
=
0.2 V
© 2012-2018 Toshiba Memory Corporation
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TC58NVG1S3HTA00
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta
=
0 to 70°C, V
CC
=
2.7 to 3.6V)
SYMBOL
t
CLS
t
CLH
t
CS
t
CH
t
WP
t
ALS
t
ALH
t
DS
t
DH
t
WC
t
WH
t
WW
t
RR
t
RW
t
RP
t
RC
t
REA
t
CEA
t
CLR
t
AR
t
RHOH
t
RLOH
t
RHZ
t
CHZ
t
CSD
t
REH
t
IR
t
RHW
t
WHC
t
WHR
t
WB
t
RST
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
WP High to WE Low
Ready to RE Falling Edge
Ready to WE Falling Edge
Read Pulse Width
Read Cycle Time
RE Access Time
CE Access Time
CLE Low to RE Low
ALE Low to RE Low
--------
--------
--------
--------
--------
--------
--------
--------
--------
--------
--------
--------
PARAMETER
MIN
12
5
20
5
12
12
5
12
5
25
10
100
20
20
12
25
10
10
25
5
0
10
MAX
20
25
60
20
100
5/5/10/500
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
RE High to Output Hold Time
RE Low to Output Hold Time
RE High to Output High Impedance
CE High to Output High Impedance
CE High to ALE or CLE Don’t Care
RE High Hold Time
Output-High-Impedance-to-RE Falling Edge
--------
--------
--------
--------
--------
--------
--------
--------
0
30
30
60
RE High to WE Low
WE High to CE Low
WE High to RE Low
--------
--------
--------
--------
--------
WE High to Busy
Device Reset Time (Ready/Read/Program/Erase)
*1: tCLS and tALS can not be shorter than tWP
*2: tCS should be longer than tWP + 8ns
© 2012-2018 Toshiba Memory Corporation
5
2018-12-14C
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