TLP2631
TOSHIBA photocoupler
GaAℓAs IRed & Photo IC
TLP2631
Isolated Line Receiver
Simplex / Multiplex Data Transmission
Computer-Peripheral Interface
Microprocessor System Interface
Digital Isolation for A / D, D / A Conversion
The TOSHIBA TLP2631 dual photocoupler consists of a pair of GaAℓAs
light emitting diode and integrated high gain, high speed photodetector.
This unit is 8-lead DIP.
The output of the detector circuit is an open collector, Schottky clamped
transistor.
A Faraday shield integrated on the photodetector chip reduces the effects
of capacitive coupling between the input LED emitter and the high gain
stages of the detector. This provides an effective common mode transient
immunity of 1000 V/μs.
•
Input current threshold: I
F
= 5 mA (max)
•
•
•
•
•
•
Switching speed: 10MBd (typ.)
Common mode transient immunity: ±1000 V/μs (min)
Guaranteed performance over temperature: 0 to 70°C
UL recognized: UL1577, file no. E67349
cUL approved :CSA Component Acceptance Service
No. 5A, File No.E67349
Isolation voltage: 2500 V
rms
(min)
TOSHIBA
11−10C4
Weight: 0.54 g (typ.)
Unit: mm
Truth Table
(positive logic)
Input
H
L
Output
L
Pin Configuration (top view)
1
V
CC
8
7
6
GND
Shield
5
1 : Anode 1
2 : Cathode 1
3 : Cathode 2
4 : Anode 2
5 : GND
6 : V
O2
(Output 2)
7 : V
O1
(Output 1)
8 : V
CC
H
2
Schematic
+
V
F1
−
+
V
F2
−
1
2
4
3
5
GND
I
F2
I
O2
6
I
F1
Shield
I
CC
I
O1
8
7
V
CC
V
O1
3
4
V
O2
A 0.01 to 0.1μF bypass capacitor must be
connected between pins 8 and 5(see Note 1).
Start of commercial production
1986-03
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TLP2631
Absolute Maximum Ratings
(no derating required up to 70°C)
Characteristic
Forward current (each channel)
Pulse forward current (each channel)*
LED
Reverse voltage (each channel)
Input power dissipation(each channel)
Input power dissipation
(each channel)
derating
(Ta
≥
70°C)
Symbol
I
F
I
FP
V
R
P
D
Rating
20
30
5
25
-0.45
16
−0.5
to 7
7
Unit
mA
mA
V
mW
mW/°C
mA
V
V
Δ
P
D
/°C
I
O
V
O
V
CC
P
O
Output current (each channel)
Output voltage (each channel)
Detector
Supply voltage
(1 minute maximum)
Output collector power
dissipation (each channel)
Output power dissipation
(each channel)
Storage temperature range
Operating temperature range
Lead soldering temperature (10s)**
Isolation voltage
(AC, 1 minute, R.H.≤ 60%, Ta=25°C
(Note 3)
derating
(Ta
≥
70°C)
40
mW
Δ
P
O
/°C
T
stg
T
opr
T
sol
BV
S
-0.75
−55
to 125
−40
to 85
260
2500
mW/°C
°C
°C
°C
Vrms
Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if
the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
* t
≤
1 msec duration.
** 2mm below seating plane.
Recommended Operating Conditions
Characteristic
Input current, low level, each channel
Input current, high level, each channel
Supply voltage**
Fan out (TTL load, each channel)
Operating temperature
Symbol
I
FL
I
FH
V
CC
N
T
opr
Min
0
6.3*
4.5
―
0
Typ.
―
―
5
―
―
Max
250
20
5.5
8
70
°C
Unit
μA
mA
V
Note: Recommended operating conditions are given as a design guideline to obtain expected performance of the
device. Additionally, each item is an independent guideline respectively. In developing designs using this
product, please confirm specified characteristics shown in this document.
*
6.3mA is a guard banded value which allows for at least 20% CTR degradation.
Initial input current threshold value is 5.0 mA or less.
** This item denotes operating ranges, not meaning of recommended operating conditions.
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TLP2631
Electrical Characteristics
(Ta = 0 to 70°C unless otherwise noted)
Characteristic
Input forward voltage
(each channel)
Input diode temperature
coefficient (each channel)
Input reverse breakdown
voltage (each channel)
Input capacitance
(each channel)
High level output current
(each channel)
Low level output voltage
(each channel)
High level supply current
(both channels)
Low level supply current
(both channels)
Isolation voltage
Capacitance (input−output)
Input−input leakage current
Resistance (input−input)
Capacitance (input−input)
Symbol
V
F
ΔV
F
/
ΔTa
BV
R
C
T
I
OH
V
OL
I
CCH
I
CCL
R
S
C
S
I
I−I
R
I−I
C
I−I
Test Condition
I
F
= 10mA, Ta = 25°C
I
F
= 10mA
I
R
= 10μA, Ta = 25°C
V
F
= 0V, f = 1MHz
V
CC
= 5.5V, V
O
= 5.5V
I
F
= 250μA
V
CC
= 5.5V, I
F
= 5mA
I
OL
(sinking) = 13mA
V
CC
= 5.5V, I
F
= 0 mA
V
CC
= 5.5V, I
F
= 10mA
V
S
= 500V, R.H.
≤
60%
f = 1MHz
R.H.
≤
60%, t = 5s
V
I−I
= 500V
V
I−I
= 500V
f = 1MHz
(Note 3)
(Note 3)
(Note 6)
(Note 6)
(Note 6)
Min
―
―
5
―
―
―
―
―
5×10
10
―
―
―
―
Typ. *
1.65
−2.0
―
45
Max
1.75
―
―
―
250
Unit
V
mV / °C
V
pF
μA
V
mA
mA
Ω
pF
μA
Ω
pF
1
0.4
14
24
10
14
0.6
0.005
10
11
0.25
0.6
30
38
―
―
―
―
―
* All typical values are at V
CC
= 5V, Ta = 25°C.
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TLP2631
Switching Characteristics
(Ta = 25°C, V
CC
= 5V)
Characteristic
Propagation delay time to
low output level
Propagation delay time to
high output level
Output rise time, output
fall time (10 to 90%)
Common mode transient
immunity at high output level
Symbol
t
p
HL
t
p
LH
t
r
, t
f
Test
Circuit
1
1
1
Test Condition
I
F
= 0→7.5mA, R
L
= 350Ω
C
L
= 15pF (each channel)
I
F
= 7.5mA→0, R
L
= 350Ω
C
L
= 15pF (each channel)
I
F
= 0 7.5mA, R
L
= 350Ω
C
L
= 15pF (each channel)
I
F
= 0 mA, R
L
= 350Ω
V
CM
= 400V,
V
O
(min.) = 2V
(each channel, Note 4)
I
F
= 7.5mA, R
L
= 350Ω
V
CM
= 400V
V
O
(max.) = 0.8V
(each channel, Note 5)
Min
―
―
―
Typ.
60
60
30
Max
75
75
―
Unit
ns
ns
ns
CM
H
2
1000
10000
―
V /
μs
Common mode transient
immunity at low output level
CM
L
2
−1000
−10000
―
V /
μs
(Note 1) 2mm below seating plane
(Note 2) The V
CC
supply voltage to each TLP2631 isolator must be bypassed by a 0.1μF capacitor or larger. This
can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be
connected as close as possible to the package V
CC
and GND pins each device.
(Note 3) Device considered a two−terminal device: Pins 1, 2, 3 and 4 shorted together, and pins 5, 6, 7 and 8
shorted together.
(Note 4) CM
H
½the
maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in
the high state (i.e. V
OUT
> 2.0V).
Measured in volts per microsecond (V /
μs).
Volts/ microsecond can be translated to sinusoidal voltages:
V /
μs
=
(dVCM)
Max.
=
fCM VCM (p.p.)
dt
Example:
V
CM
= 319V
pp
when f
CM
= 1MHz using CM
L
and CM
H
= 1000V /
μs
data sheet specified minimum.
(Note 5) CM
L
½the
maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in
the low output state (i.e. V
OUT
< 0.8V).
Measured in volts per microsecond (V /
μs).
(Note 6) Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together.
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2017-08-21
TLP2631
Test Circuit 1. t
p
HL and t
p
LH
5V
Pulse input
PW = 10μs
Duty cycle = 1/10
I
F
Monitor
100Ω
1
2
3
4
V
CC
8
0.1μF
7
6
GND 5
R
L
350Ω
C
L
V
O
Monitor
V
O
1.5V
0.5V
V
OL
I
F
t
r
t
f
5V
4.5V
7.5mA
3.75mA
0mA
* C
L
is approximately 15pF which includes probe and stray
wiring capacitance.
t
pHL
t
pLH
Test Circuit 2. Transient Immunity and Typical Waveforms
I
F
1
2
A
B
V
FF
3
4
V
CC
8
0.1μF
7
6
5V
R
L
350Ω
V
O
Monitor
V
CM
90%
10%
t
r
t
f
400V
0V
GND 5
V
CM
C
L
V
O
(I
F
= 0mA)
5V
2V
0.8V
+
Z
O =
50Ω
−
V
O
(I
F
= 7.5mA)
Pulse generator
V
OL
CMH
=
320(V)
320(V)
,
CML
=
t r
(
μs
)
t r
(
μs
)
*
C
L
is approximately 15pF which includes probe and stray
wiring capacitance.
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2017-08-21
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