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EBE51ED8ABFA-4C

Description
DDR DRAM Module, 64MX72, 0.6ns, CMOS, DIMM-240
Categorystorage   
File Size170KB,22 Pages
ManufacturerELPIDA
Websitehttp://www.elpida.com/en
Download Datasheet Parametric Compare View All

EBE51ED8ABFA-4C Overview

DDR DRAM Module, 64MX72, 0.6ns, CMOS, DIMM-240

EBE51ED8ABFA-4C Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerELPIDA
Parts packaging codeDIMM
package instructionDIMM, DIMM240,40
Contacts240
Reach Compliance Codeunknown
ECCN codeEAR99
Is SamacsysN
access modeSINGLE BANK PAGE BURST
Maximum access time0.6 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)200 MHz
I/O typeCOMMON
JESD-30 codeR-XDMA-N240
memory density4831838208 bit
Memory IC TypeDDR DRAM MODULE
memory width72
Humidity sensitivity level1
Number of functions1
Number of ports1
Number of terminals240
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64MX72
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeDIMM
Encapsulate equivalent codeDIMM240,40
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)225
power supply1.8 V
Certification statusNot Qualified
refresh cycle16384
self refreshYES
Maximum supply voltage (Vsup)1.9 V
Minimum supply voltage (Vsup)1.7 V
Nominal supply voltage (Vsup)1.8 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal pitch1 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Base Number Matches1
PRELIMINARY DATA SHEET
512MB Unbuffered DDR2 SDRAM DIMM
EBE51ED8ABFA
(64M words
×
72 bits, 1 Rank)
Description
The EBE51ED8ABFA is 64M words
×
72 bits, 1 rank
DDR2 SDRAM unbuffered module, mounting 9 pieces
of 512M bits DDR2 SDRAM sealed in FBGA (µBGA
)
package. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 4 bits prefetch-
pipelined architecture. Data strobe (DQS and /DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. This module provides high
density mounting without utilizing surface mount
technology.
Decoupling capacitors are mounted
beside each FBGA (µBGA) on the module board.
Note: Do not push the components or drop the
modules in order to avoid mechanical defects,
which may result in electrical defects.
Features
240-pin socket type dual in line memory module
(DIMM)
PCB height: 30.0mm
Lead pitch: 1.0mm
1.8V power supply
Data rate: 533Mbps/400Mbps (max.)
1.8V (SSTL_18 compatible) I/O
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
(components)
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
7.8µs average periodic refresh interval
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
/DQS can be disabled for single-ended Data Strobe
operation
Document No. E0378E20 (Ver. 2.0)
Date Published November 2003 (K) Japan
URL: http://www.elpida.com
Elpida
Memory, Inc. 2003

EBE51ED8ABFA-4C Related Products

EBE51ED8ABFA-4C EBE51ED8ABFA-4A EBE51ED8ABFA-5C
Description DDR DRAM Module, 64MX72, 0.6ns, CMOS, DIMM-240 DDR DRAM Module, 64MX72, 0.6ns, CMOS, DIMM-240 DDR DRAM Module, 64MX72, 0.5ns, CMOS, DIMM-240
Is it Rohs certified? incompatible incompatible incompatible
Maker ELPIDA ELPIDA ELPIDA
Parts packaging code DIMM DIMM DIMM
package instruction DIMM, DIMM240,40 DIMM, DIMM240,40 DIMM, DIMM240,40
Contacts 240 240 240
Reach Compliance Code unknown unknown unknown
ECCN code EAR99 EAR99 EAR99
access mode SINGLE BANK PAGE BURST SINGLE BANK PAGE BURST SINGLE BANK PAGE BURST
Maximum access time 0.6 ns 0.6 ns 0.5 ns
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
Maximum clock frequency (fCLK) 200 MHz 200 MHz 267 MHz
I/O type COMMON COMMON COMMON
JESD-30 code R-XDMA-N240 R-XDMA-N240 R-XDMA-N240
memory density 4831838208 bit 4831838208 bit 4831838208 bit
Memory IC Type DDR DRAM MODULE DDR DRAM MODULE DDR DRAM MODULE
memory width 72 72 72
Number of functions 1 1 1
Number of ports 1 1 1
Number of terminals 240 240 240
word count 67108864 words 67108864 words 67108864 words
character code 64000000 64000000 64000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 70 °C 70 °C 70 °C
organize 64MX72 64MX72 64MX72
Output characteristics 3-STATE 3-STATE 3-STATE
Package body material UNSPECIFIED UNSPECIFIED UNSPECIFIED
encapsulated code DIMM DIMM DIMM
Encapsulate equivalent code DIMM240,40 DIMM240,40 DIMM240,40
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius) 225 235 235
power supply 1.8 V 1.8 V 1.8 V
Certification status Not Qualified Not Qualified Not Qualified
refresh cycle 16384 16384 16384
self refresh YES YES YES
Maximum supply voltage (Vsup) 1.9 V 1.9 V 1.9 V
Minimum supply voltage (Vsup) 1.7 V 1.7 V 1.7 V
Nominal supply voltage (Vsup) 1.8 V 1.8 V 1.8 V
surface mount NO NO NO
technology CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form NO LEAD NO LEAD NO LEAD
Terminal pitch 1 mm 1 mm 1 mm
Terminal location DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED 30 30
Is Samacsys N N -
Base Number Matches 1 1 -

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