ACTS630D/SAMPLE datasheet, PDF

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ACTS630D/SAMPLE: DescriptionACT SERIES, 16-BIT ERROR DETECT AND CORRECT CKT, CDIP28, SIDE BRAZED, CERAMIC, DIP-28; Categorylogic; File Size316KB，3 Pages; ManufacturerRenesas Electronics Corporation; Websitehttps://www.renesas.com/

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ACTS630D/SAMPLE Overview

ACT SERIES, 16-BIT ERROR DETECT AND CORRECT CKT, CDIP28, SIDE BRAZED, CERAMIC, DIP-28

ACTS630D/SAMPLE Parametric

Parameter Name	Attribute value
Maker	Renesas Electronics Corporation
Parts packaging code	DIP
package instruction	DIP,
Contacts	28
Reach Compliance Code	unknown
Is Samacsys	N
series	ACT
JESD-30 code	R-CDIP-T28
Logic integrated circuit type	ERROR DETECTION AND CORRECTION CIRCUIT
Number of digits	16
Number of functions	1
Number of terminals	28
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
propagation delay (tpd)	37 ns
Certification status	Not Qualified
Maximum seat height	5.92 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	15.24 mm
Base Number Matches	1

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TM

ACTS630MS

Radiation Hardened EDAC

(Error Detection and Correction)

Pinouts

28 PIN CERAMIC DUAL-IN-LINE, MIL-STD-1835

DESIGNATOR CDIP-T28, LEAD FINISH C

TOP VIEW

DEF 1

DB0 2

DB1 3

DB2 4

28 VCC

27 SEF

26 S1

25 S0

24 CB0

23 CB1

22 CB2

21 CB3

20 CB4

19 CB5

18 DB15

17 DB14

16 DB13

15 DB12

January 1996

Features

• Devices QML Qualified in Accordance with MIL-PRF-38535

• Detailed Electrical and Screening Requirements are Contained in

SMD# 5962-96721 and Intersil’s QM Plan

itle

CTS

0MS

b-

t

adia-

n

rd-

ed

AC

rror

tec-

n

d

r-

-

n))

thor

ey-

rds

ter-

rpo-

ion,

dia-

n

rd-

ed,

,

d

rd,

L,

tel-

,

• 1.25 Micron Radiation Hardened SOS CMOS

• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)

• Single Event Upset (SEU) Immunity: <1 x 10

(Typ)

-10

Errors/Bit/Day

MEV-cm

2

/mg

• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100

DB3 5

DB4 6

DB5 7

DB6 8

DB7 9

DB8 10

DB9 11

DB10 12

DB11 13

GND 14

• Dose Rate Upset . . . . . . . . . . . . . . . . >10

11

RAD (Si)/s, 20ns Pulse

• Dose Rate Survivability . . . . . . . . . . . >10

12

RAD (Si)/s, 20ns Pulse

• Latch-Up Free Under Any Conditions

• Military Temperature Range . . . . . . . . . . . . . . . . . . -55

o

C to +125

o

C

• Significant Power Reduction Compared to ALSTTL Logic

• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V

• Input Logic Levels

- VIL = 0.8V Max

- VIH = VCC/2 Min

• Input Current

≤

1µA at VOL, VOH

• Fast Propagation Delay . . . . . . . . . . . . . . . . 37ns (Max), 24ns (Typ)

Description

The Intersil ACTS630MS is a Radiation Hardened 16-bit parallel error

detection and correction circuit. It uses a modified Hamming code to gen-

erate a 6-bit check word from each 16-bit data word. The check word is

stored with the data word during a memory write cycle; during a memory

read cycle a 22-bit word is taken form memory and checked for errors.

Single bit errors in the data words are flagged and corrected. Single bit

errors in check words are flagged but not corrected. The position of the

incorrect bit is pinpointed, in both cases, by the 6-bit error syndrome

code which is output during the error correction cycle.

The ACTS630MS utilizes advanced CMOS/SOS technology to achieve

high-speed operation. This device is a member of a radiation hardened,

high-speed, CMOS/SOS Logic Family.

The ACTS630MS is supplied in a 28 lead Ceramic Flatpack (K suffix) or

a 28 Lead Ceramic Dual-In-Line Package (D suffix).

28 PIN CERAMIC FLATPACK, MIL-STD-1835

DESIGNATOR CDFP3-F28, LEAD FINISH C

TOP VIEW

DEF

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

DB10

DB11

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VCC

SEF

S1

S0

CB0

CB1

CB2

CB3

CB4

CB5

DB15

DB14

DB13

DB12

Ordering Information

PART NUMBER

5962F9672101VXC

5962F9672101VYC

ACTS630D/Sample

ACTS630K/Sample

ACTS630HMSR

TEMPERATURE RANGE

-55

o

C to +125

o

C

-55

o

C to +125

o

C

25

o

C

25

o

C

25

o

C

SCREENING LEVEL

MIL-PRF-38535 Class V

Sample

Die

PACKAGE

28 Lead SBDIP

28 Lead Ceramic Flatpack

28 Lead SBDIP

28 Lead Ceramic Flatpack

Die

1-888-INTERSIL or 321-724-7143

|

Intersil and Design is a trademark of Intersil Americas Inc.

Spec Number

File Number

1

518786

3204.1

ACTS630D/SAMPLE Related Products

	ACTS630D/SAMPLE	ACTS630K/SAMPLE
Description	ACT SERIES, 16-BIT ERROR DETECT AND CORRECT CKT, CDIP28, SIDE BRAZED, CERAMIC, DIP-28	ACT SERIES, 16-BIT ERROR DETECT AND CORRECT CKT, CDFP28, CERAMIC, DFP-28
Maker	Renesas Electronics Corporation	Renesas Electronics Corporation
Parts packaging code	DIP	DFP
package instruction	DIP,	DFP,
Contacts	28	28
Reach Compliance Code	unknown	unknown
series	ACT	ACT
JESD-30 code	R-CDIP-T28	R-CDFP-F28
Logic integrated circuit type	ERROR DETECTION AND CORRECTION CIRCUIT	ERROR DETECTION AND CORRECTION CIRCUIT
Number of digits	16	16
Number of functions	1	1
Number of terminals	28	28
Output characteristics	3-STATE	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP	DFP
Package shape	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	FLATPACK
propagation delay (tpd)	37 ns	37 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	5.92 mm	2.92 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V
Minimum supply voltage (Vsup)	4.5 V	4.5 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	NO	YES
technology	CMOS	CMOS
Terminal form	THROUGH-HOLE	FLAT
Terminal pitch	2.54 mm	1.27 mm
Terminal location	DUAL	DUAL
width	15.24 mm	12.445 mm

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