a
FEATURES
Programmable “Quality Box”
Industrial Temperature Range (ADV612)
Hardware Frame Rate Reduction
100% Bitstream Compatible with the ADV601 and
ADV601LC
Precise Compressed Bit Rate Control
Field Independent Compression
8-Bit Video Interface Supports CCIR-656 and Multi-
plexed Philips Formats
General Purpose 16- or 32-Bit Host Interface with
512 Deep 32-Bit FIFO
PERFORMANCE
Real-Time Compression or Decompression of CCIR-601
to Video:
720 288 @ 50 Fields/Sec — PAL
720 243 @ 60 Fields/Sec — NTSC
Compression Ratios from Visually Loss-Less to 7500:1
Visually Loss-Less Compression At 4:1 on Natural
Images (Typical)
APPLICATIONS
CCTV Cameras and Systems
Time-Lapse Video Tape Recorders
Time-Lapse Video Disk Recorders
Wireless CCTV Cameras
Fiber CCTV Systems
GENERAL DESCRIPTION
Closed Circuit TV Digital
Video Codec
ADV611/ADV612
levels. The chips integrate glueless video and host interfaces
with on-chip SRAM to permit low part count, system level
implementations suitable for a broad range of applications.
The ADV611/ADV612 are 100% bitstream compatible with
the ADV601. The ADV611/ADV612 comes in a 120-lead
LQFP package.
The ADV611/ADV612 are video encoders/decoders optimized
for closed circuit TV (CCTV) applications. With the ADV611/
ADV612, you can define a portion of each video field to be at a
higher quality level relative to the rest of the field. This “quality
box” feature significantly increases compression of less impor-
tant background details, while retaining the image’s overall
context. Additionally, the unique subband coding architecture
of the ADV611/ADV612 offer many application-specific
advantages. A review of the General Theory of Operation and
Applying the ADV611/ADV612 sections will help you get the
most use out of the ADV611/ADV612 in any given application.
The ADV611/ADV612 accept component digital video through
the Video Interface and outputs a compressed bitstream though the
Host Interface in Encode Mode. While in Decode Mode, the
ADV611/ADV612 accept compressed bitstream through the Host
Interface and outputs component digital video through the Video
Interface. The host accesses all of the ADV611/ADV612’s control
and status registers using the Host Interface. Figure 2 summarizes
the basic function of the part.
(continued on page 2)
ANALOG
VIDEO
SIGNAL
OR
IMAGE
SENSOR
SIGNAL
DIGITIZER
ADV7185
DECODER
SERIAL
OR PARALLEL
BITSTREAM FOR
TRANSMISSION
OR STORAGE
The ADV611/ADV612 are low cost, single chip, dedicated func-
tion, all-digital-CMOS-VLSI devices capable of supporting
visually loss-less to 7500:1 real-time compression and decom-
pression of CCIR-601 digital video at very high image quality
ADV611/
ADV612
ADSP-21xx
QUALITY BOX CONTROLS
FROM REMOTE SITE
Figure 1. Typical Application
FUNCTIONAL BLOCK DIAGRAM
LOCATION, SIZE AND CONTRAST CONTROL
ADV611/
ADV612
ON-CHIP
TRANSFORM
BUFFER
WAVELET
FILTERS,
DECIMATOR &
INTERPOLATOR
DRAM
MANAGER
SUBBAND STATISTICS
COMPONENT
VIDEO I/O
8
DIGITAL
VIDEO
I/O PORT
QUALITY
BOX
CONTROL
QUANTIZER
& ENTROPY
CODING
HOST
I/O PORT
& FIFO
16/32
HOST
BIN WIDTH CONTROL
256K
16-BIT DRAM
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
ADV611/ADV612
TABLE OF CONTENTS
GENERAL DESCRIPTION
(Continued
from page 1)
VIDEO INTERFACE
DIGITAL VIDEO IN
(ENCODE)
DIGITAL VIDEO
OUT (DECODE)
This data sheet gives an overview of the ADV611/ADV612’s
functionality and provides details on designing the part into a
system. The text of the data sheet is written for an audience with
a general knowledge of designing digital video systems. Where
appropriate, additional sources of reference material are noted
throughout the data sheet.
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
COMPARING THE ADV6xx FAMILY VIDEO CODECS . . . . . 3
INTERNAL ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . 4
GENERAL THEORY OF OPERATION . . . . . . . . . . . . . . . . . . 4
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
THE WAVELET KERNEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
THE PROGRAMMABLE QUANTIZER . . . . . . . . . . . . . . . . . 8
THE RUN LENGTH CODER AND HUFFMAN CODER . . . . . 9
Encoding vs. Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PROGRAMMER’S MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
ADV611/ADV612 REGISTER DESCRIPTIONS . . . . . . . . . . 11
VIDEO AREA REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . 18
Video Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Video Formats–CCIR-656 . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DRAM Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Compressed Data-Stream Definition . . . . . . . . . . . . . . . . . . . 24
APPLYING THE ADV611/ADV612 . . . . . . . . . . . . . . . . . . . . 30
Using the ADV611/ADV612 in Computer Applications . . . . . . 30
Using the ADV611/ADV612 in Stand-Alone Applications . . . . 31
Connecting the ADV611/ADV612 to Popular Video
Decoders and Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
GETTING THE MOST OUT OF ADV611/ADV612 . . . . . . . 32
How Much Compression Can Be Expected . . . . . . . . . . . . . . 32
Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Software Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Field Rate Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Edge Enhancement and Detection . . . . . . . . . . . . . . . . . . . . . 32
Motion Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ADV611/ADV612 SPECIFICATIONS . . . . . . . . . . . . . . . . . . 33
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
TIMING PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Clock Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
CCIR-656 Video Format Timing . . . . . . . . . . . . . . . . . . . . . . 35
Multiplexed Philips Video Timing . . . . . . . . . . . . . . . . . . . . . 37
Host Interface (Indirect Address, Indirect Register Data,
and Interrupt Mask/Status) Register Timing . . . . . . . . . . . 40
Host Interface (Compressed Data) Register Timing . . . . . . . 42
ADV611/ADV612 LQFP PINOUTS . . . . . . . . . . . . . . . . . . . . 44
ADV611/ADV612 PIN CONFIGURATION . . . . . . . . . . . . . . 45
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
HOST INTERFACE
ADV611/
ADV612
VIDEO CODEC
CCTV DIGITAL
COMPRESSED
VIDEO OUT
(ENCODE)
STATUS AND CONTROL
COMPRESSED VIDEO
IN (DECODE)
Figure 2. Functional Block Diagram
The ADV611/ADV612 adheres to international standard
CCIR-601 for studio quality digital video. The codec also sup-
ports a range of field sizes and rates providing high performance
in computer, PAL, NTSC, or still image environments. The
ADV611/ADV612 is designed only for real-time interlaced
video; full frames of video are formed and processed as two
independent fields of data. The ADV611/ADV612 supports the
field rates and sizes in Table I. Note that the maximum active
field size is 720 by 288. The maximum pixel rate is 13.50 MHz.
The ADV611/ADV612 has a generic 16-/32-bit host interface
that includes a 512-position, 32-bit wide FIFO for compressed
video. With additional external hardware, the ADV611/ADV612’s
host interface is suitable (when interfaced to other devices) for
moving compressed video over PCI, ISA, SCSI, SONET, 10 Base
T, ARCnet, HDSL, ADSL and a broad range of digital inter-
faces. For a full description of the Host Interface, see the Host
Interface section.
The compressed data rate is determined by the input data rate
and the selected compression ratio. The ADV611/ADV612 can
achieve a near constant compressed bit rate by using the current
field statistics in the off-chip bin width calculator on the exter-
nal DSP or Host. The process of calculating bin widths on a
DSP or Host can be “adaptive,” optimizing the compressed bit
rate in real time. This feature provides a near constant bit rate
out of the host interface in spite of scene changes or other types
of source material changes that would otherwise create bit rate
burst conditions. For more information on the quantizer, see
the Programmable Quantizer section.
The ADV611/ADV612 typically yields visually loss-less com-
pression on natural images at a 4:1 compression ratio. For more
information on compression ratios, see the Getting the Most
Out of the ADV611/ADV612 section. Desired image quality
levels can vary widely in different applications, so it is advisable
to evaluate image quality of known source material at different
compression ratios to find the best compression range for the
application. The subband coding architecture of the ADV611/
ADV612 provides a number of options to stretch compression
performance. These options are outlined in the Applying the
ADV611/ADV612 section.
Table I. ADV611/ADV612 Field Rates and Sizes
Standard
Name
CCIR-601/525
CCIR-601/625
Active
Region
Horizontal
720
720
Active
Region
Vertical
1
243
288
Total
Region
Horizontal
858
864
Total
Region
Vertical
262.5
312.5
Field Rate
(Hz)
59.94
50.00
Pixel Rate
(MHz)
2
13.50
13.50
NOTES
1
The maximum active field size is 720 by 288.
2
The maximum pixel rate is 13.5 MHz.
–2–
REV. 0
ADV611/ADV612
Original Video Image
Image after compression/decompression shown
with different box size and position
PROGRAMMABLE
QUALITY BOX
VARIABLE CONTRAST
BACKGROUND
Figure 3.
The ADV611/ADV612 are real-time compression integrated
circuits designed for remote video surveillance or closed circuit
television (CCTV) applications. The most important feature of
these two devices is the “Quality Box.” With this feature the
user can define a box of any size and location within each field
of video that will be compressed at full contrast while the re-
mainder outside the box, or background of the image, is com-
pressed at a lower level of contrast. The background contrast
level is controlled by the user. The lower the contrast level, the
more the image will be compressed. The objective in a given
application is to adjust the background contrast to a level that
ensures both a recognizable and useful background as well as
the highest possible compression. Figure 3 shows how this qual-
ity box appears in final video.
The ADV611/ADV612 is housed in a plastic LQFP package
suitable for cost-sensitive commercial applications.
COMPARING THE ADV6xx FAMILY VIDEO CODECS
The ADV6xx video codecs support a range of interface, pack-
age, and compression features. Table II compares these codecs:
Table II. Differences Between the ADV601, ADV601LC, ADV611 and ADV612
ADV601
Bits per Component
DSP Serial Port
Package
Pin Assignments
Temperature Range
θ
JA
θ
JC
Field Rate Reduction
Stall Mode
Field Truncation
Field Size Register
Field Bit Polarity Control
Evaluation Board
Target Applications
10
Yes
160 PQFP
Unique
0°C to +70°C
31°C/W
7.5°C/W
Software
No
No
No
No
VideoLab
Professional
ADV601LC
8
No
120 LQFP
Unique
0°C to +70°C
35°C/W
5°C/W
Software
No
No
No
No
VideoPipe
Consumer
ADV611
8
No
120 LQFP
98% Similar to ADV601LC
0°C to +70°C
35°C/W
5°C/W
Hardware
Yes
Yes
Yes
Yes
CCTVPIPE
CCTV
ADV612
8
No
120 LQFP
98% Similar to ADV601LC
–25°C to +85°C
35°C/W
5°C/W
Hardware
Yes
Yes
Yes
Yes
CCTVPIPE
Industrial CCTV
REV. 0
–3–
ADV611/ADV612
INTERNAL ARCHITECTURE
Programmable Quantizer
The ADV611/ADV612 is composed of eight blocks. Three of
these blocks are interface blocks and five are processing blocks.
The interface blocks are the Digital Video I/O Port, the Host
I/O Port and the external DRAM manager. The processing
blocks are the Wavelet Kernel, the On-Chip Transform Buffer,
the Programmable Quantizer, the Run Length Coder and the
Huffman Coder.
Digital Video I/O Port
Quantizes wavelet coefficients. Quantize controls are calculated
by the external DSP or host processor during encode operations
and de-quantize controls are extracted from the compressed
bitstream during decode. Each quantizer Bin Width is com-
puted by the BW calculator software to maintain a constant
compressed bit rate or constant quality bit rate. A Bin Width is
a per-block parameter the quantizer uses when determining the
number of bits to allocate to each block (subband).
Quality Box
Provides a real-time uncompressed video interface to support a
broad range of component digital video formats, including “D1.”
Host I/O Port and FIFO
Carries control, status, and compressed video to and from the
host processor. A 512 position by 32-bit FIFO buffers the com-
pressed video stream between the host and the Huffman Coder.
Hardware Field Rate Reduction
In CCTV applications it is often desirable to reduce the field
rate to achieve the highest possible compression. The ADV611/
ADV612 have special hardware to permit this function. It is
possible to set a register on the ADV611/ADV612 during en-
code mode that will automatically reduce the field rate. This is a
5-bit register that allows up to 31 fields to be “skipped.”
Stall Mode
The quality box is defined using the Video Area Registers that
are described in the Registers Descriptions section. The back-
ground contrast is controlled using Background Contrast Regis-
ters that are defined later in this document. It is possible to
control both parameters on a per-field basis during Encode
Mode. This enables the quality box to either move slowly across
the image or to instantaneously jump from one location to the
next.
Run Length Coder
Performs run length coding on zero data and models nonzero
data, encoding or decoding for more efficient Huffman coding.
This data coding is optimized across the subbands and varies
depending on the block being coded.
Huffman Coder
It is possible to stall or halt the ADV611/ADV612 at any time
during Encode Mode. This allows the user to feed uncompressed
video data to these parts and to stop indefinitely between fields
or even between pixels. This feature is useful when compressing
video that is not coming into the ADV611/ADV612 at sustained
V
CLK
rates. Stall Mode is enabled by asserting the Stall pin at
any time during encode. Stall mode is enabled on the next clock
cycle after the pin is asserted.
Field Size Reporting
Performs Huffman coder and decoder functions on quantized
run-length coded coefficient values. The Huffman coder/de-
coder uses three ROM-coded Huffman tables that provide ex-
cellent performance for wavelet transformed video.
Field Truncation
The ADV611/ADV612 have a read-only register that allows the
user to read the field size of the most recently compressed field.
This feature is useful in the feedback loop of a precise bit rate
controller. The data is valid after LCODE (unless an entire
compressed field resides in the internal FIFO).
DRAM Manager
Performs all tasks related to writing, reading and refreshing the
external DRAM. The external host buffer DRAM is used for
reordering and buffering quantizer input and output values.
Wavelet Kernel (Filters, Decimator, and Interpolator)
It is possible to set a hard upper limit to the field size of each
field during Encode Mode. The Huffman Coder is able to de-
tect if the field size exceeds a preset threshold and then causes
the remaining Mallat block data to be zeroed out, therefore,
truncating the field’s data. The bitstream is truncated in such a
way that all end-of-field markers are inserted. This means that
the compressed bitstream can still be decompressed by any
hardware or software ADV6xx decoder. The only penalty is the
loss of Mallat blocks which, depending on how many are lost,
will degrade the image quality of the truncated field.
GENERAL THEORY OF OPERATION
Gathers statistics on a per-field basis and includes a block of
filters, interpolators and decimators. The kernel calculates for-
ward and backward bi-orthogonal, two-dimensional, separable
wavelet transforms on horizontal scanned video data. This block
uses the internal transform buffer when performing wavelet
transforms calculated on an entire image’s data and so elimi-
nates any need for extremely fast external memories in an
ADV611/ADV612-based design.
On-Chip Transform Buffer
The ADV611/ADV612 processor’s compression algorithm is
based on the bi-orthogonal (7, 9) wavelet transform, and imple-
ments field independent subband coding. Subband coders trans-
form two-dimensional spatial video data into spatial frequency
filtered subbands. The quantization and entropy encoding pro-
cesses provide the ADV611/ADV612’s data compression.
The wavelet theory, on which the ADV611/ADV612 is based, is
a new mathematical apparatus first explicitly introduced by
Morlet and Grossman in their works on geophysics during the
mid 80s. This theory became very popular in theoretical physics
and applied math. The late 80s and 90s have seen a dramatic
growth in wavelet applications such as signal and image process-
ing. For more on wavelet theory by Morlet and Grossman, see
Decomposition of Hardy Functions into Square Integrable Wavelets
of Constant Shape
(journal citation listed in References section).
Provides an internal set of SRAM for use by the wavelet trans-
form kernel. Its function is to provide enough delay line storage
to support calculation of separable two dimensional wavelet
transforms for horizontally scanned images.
–4–
REV. 0
ADV611/ADV612
ENCODE
PATH
DECODE
PATH
WAVELET
KERNEL
FILTER BANK
ADAPTIVE
QUANTIZER
RUN LENGTH
CODER &
HUFFMAN
CODER
COMPRESSED
DATA
image processing, scaling, and a number of other system fea-
tures possible with little or no computational overhead.
The resultant filtered image is made up of components of the
original image as is shown in Figure 5 (a modified Mallat Tree).
Note that Figure 5 shows how a component of video would be
filtered, but in multiple component video, luminance and color
components are filtered separately. In Figure 6 and Figure 7 an
actual image and the Mallat Tree (luminance only) equivalent is
shown. It is important to note that while the image has been
filtered or transformed into the frequency domain, no compres-
sion has occurred. With the image in its filtered state, it is now
ready for processing in the second block, the quantizer.
Understanding the structure and function of the wavelet filters
and resultant product is the key to obtaining the highest perfor-
mance from the ADV611/ADV612. Consider the following
points:
•
The data in all blocks (except N) for all components are high
pass filtered. Therefore, the mean pixel value in those blocks
is typically zero and a histogram of the pixel values in these
blocks will contain a single “hump” (Laplacian distribution).
•
The data in most blocks is more likely to contain zeros or
strings of zeros than unfiltered image data.
•
The human visual system is less sensitive to higher frequency
blocks than low ones.
•
Attenuation of the selected blocks in luminance or color com-
ponents results in control over sharpness, brightness, contrast
and saturation.
•
High quality filtered/decimated images can be extracted/created
without computational overhead.
Through leverage of these key points, the ADV611/ADV612
not only compresses video, but offers a host of application
features. Please see the Applying the ADV611/ADV612 section
for details on getting the most out of the ADV611/ADV612’s
subband coding architecture in different applications.
Figure 4. Encode and Decode Paths
References
For more information on the terms, techniques and underlying
principles referred to in this data sheet, you may find the follow-
ing reference texts useful. A reference text for general digital
video principles is:
Jack, K.,
Video Demystified: A Handbook for the Digital Engineer
(High Text Publications, 1993) ISBN 1-878707-09-4
Three reference texts for wavelet transform background infor-
mation are:
Vetterli, M., Kovacevic, J.,
Wavelets And Subband Coding
(Prentice Hall, 1995) ISBN 0-13-097080-8
Benedetto, J., Frazier, M.,
Wavelets: Mathematics And Applica-
tions
(CRC Press, 1994) ISBN 0-8493-8271-8
Grossman, A., Morlet, J.,
Decomposition of Hardy Functions into
Square Integrable Wavelets of Constant Shape,
Siam. J. Math.
Anal., Vol. 15, No. 4, pp 723-736, 1984
THE WAVELET KERNEL
This block contains a set of filters and decimators that work on
the image in both horizontal and vertical directions. Figure 8
illustrates the filter tree structure. The filters apply carefully
chosen wavelet basis functions that better correlate to the broad-
band nature of images than the sinusoidal waves used in Dis-
crete Cosine Transform (DCT) compression schemes (JPEG,
MPEG, and H261).
An advantage of wavelet-based compression is that the entire
image can be filtered without being broken into sub-blocks as
required in DCT compression schemes. This full image filtering
eliminates the block artifacts seen in DCT compression and
offers more graceful image degradation at high compression
ratios. The availability of full image subband data also makes
N
M
J
L
K
I
F
H
C
G
E
A
D
B
BLOCK A IS HIGH PASS IN X AND DECIMATED BY TWO.
BLOCK B IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK C IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK D IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY EIGHT.
BLOCK E IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.
BLOCK F IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 32.
BLOCK G IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 32.
BLOCK H IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.
BLOCK I IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 128.
BLOCK J IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128.
BLOCK K IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.
BLOCK L IS HIGH PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.
BLOCK M IS LOW PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 512.
BLOCK N IS LOW PASS IN X, LOW PASS IN Y, AND DECIMATED BY 512.
Figure 5. Modified Mallat Diagram (Block Letters Correspond to Those in Filter Tree)
REV. 0
–5–
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