PPC5553AZQ80 datasheet, PDF - EEWORLD Datasheet

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PPC5553AZQ80: DescriptionIC,MICROCONTROLLER,32-BIT,CMOS,BGA,324PIN,PLASTIC; Categorysemiconductor The embedded processor and controller; File Size2MB，60 Pages; ManufacturerFREESCALE (NXP)

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PPC5553AZQ80 Overview

IC,MICROCONTROLLER,32-BIT,CMOS,BGA,324PIN,PLASTIC

PPC5553AZQ80 Parametric

Parameter Name	Attribute value
Number of terminals	324
Minimum operating temperature	-40 Cel
Maximum operating temperature	125 Cel
Line speed	132 MHz
each_compli	Yes
state	Contact Mfr
Number of digits	32
jesd_30_code	S-PBGA-B324
jesd_609_code	e0
moisture_sensitivity_level	3
Packaging Materials	PLASTIC/EPOXY
ckage_code	BGA
ckage_equivalence_code	BGA324,22X22,40
packaging shape	SQUARE
Package Size	GRID ARRAY
eak_reflow_temperature__cel_	245
wer_supplies	1.5,3.3,5
qualification_status	COMMERCIAL
m__bytes_	65536
ROM programming	FLASH
m__words_	1572864
sub_category	Microcontrollers
surface mount	YES
Craftsmanship	CMOS
Temperature level	Automotive
terminal coating	TIN LEAD SILVER
Terminal form	BALL
Terminal spacing	1 mm
Terminal location	BOTTOM
ime_peak_reflow_temperature_max__s_	NOT SPECIFIED

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Freescale Semiconductor

Data Sheet: Product Preview

Document Number: MPC5553

Rev. 0, 06/2006

MPC5553 Microcontroller

Data Sheet

by: Microcontroller Division

This document provides electrical specifications, pin

assignments, and package diagrams for the MPC5553

microcontroller device. For functional characteristics,

refer to the MPC5553/MPC5554

Microcontroller

Reference Manual.

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3.2 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . 5

3.3 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4 EMI (Electromagnetic Interference) Characteristics 9

3.5 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 9

3.6 VRC/POR Electrical Specifications . . . . . . . . . . . . 10

3.7 Power Up/Down Sequencing. . . . . . . . . . . . . . . . . 11

3.8 DC Electrical Specifications. . . . . . . . . . . . . . . . . . 13

3.9 Oscillator & FMPLL Electrical Characteristics . . . . 19

3.10 eQADC Electrical Characteristics . . . . . . . . . . . . . 20

3.11 H7Fa Flash Memory Electrical Characteristics . . . 21

3.12 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.13 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.14 Fast Ethernet AC Timing Specifications . . . . . . . . 45

Mechanicals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.1 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.2 Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . 55

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Overview

The MPC5553 microcontroller (MCU) is a member of

the MPC5500 family of microcontrollers based on the

PowerPC™ Book E architecture. This family of parts

contains many new features coupled with high

performance CMOS technology to provide substantial

reduction of cost per feature and significant performance

improvement over the MPC500 family.

The host processor core of this device is compatible with

the PowerPC Book E architecture. It is 100% user mode

compatible (with floating point library) with the classic

PowerPC instruction set. The Book E architecture has

enhancements that improve the PowerPC architecture’s

fit in embedded applications. This core also has

additional instructions, including digital signal

processing (DSP) instructions, beyond the classic

This document contains information on a new product. Specifications and information herein

are subject to change without notice.

•

Preliminary—Subject to Change Without Notice

Overview

PowerPC instruction set. This family of parts contains many new features coupled with high performance

CMOS technology to provide significant performance improvement over the MPC565.

The MPC5553 of the MPC5500 family has two levels of memory hierarchy. The fastest accesses are to the

8-kilobyte unified cache. The next level in the hierarchy contains the 64-kilobyte on-chip internal SRAM

and 1.5 Mbyte internal Flash memory. Both the internal SRAM and the Flash memory can hold

instructions and data. The external bus interface has been designed to support most of the standard

memories used with the MPC5xx family.

The complex I/O timer functions of the MPC5500 family are performed by an enhanced time processor

unit engine (eTPU). The eTPU engine controls 32 hardware channels. The eTPU has been enhanced over

the TPU by providing 24-bit timers, double action hardware channels, variable number of parameters per

channel, angle clock hardware, and additional control and arithmetic instructions. The eTPU can be

programmed using a high-level programming language.

The less complex timer functions of the MPC5500 family are performed by the enhanced modular

input/output system (eMIOS). The eMIOS’ 24 hardware channels are capable of single action, double

action, pulse width modulation (PWM), and modulus counter operation. Motor control capabilities include

edge-aligned and center-aligned PWM.

Off-chip communication is performed by a suite of serial protocols including controller area networks

(FlexCANs), enhanced deserial/serial peripheral interfaces (DSPI), and enhanced serial communications

interfaces (eSCIs). The DSPIs support pin reduction through hardware serialization and deserialization of

timer channels and general-purpose input/output (GPIO) signals.

The MCU of the MPC5553 has an on-chip 40-channel enhanced queued dual analog-to-digital converter

(eQADC).

The system integration unit (SIU) performs several chip-wide configuration functions. Pad configuration

and general-purpose input and output (GPIO) are controlled from the SIU. External interrupts and reset

control are also found in the SIU. The internal multiplexer submodule (SIU_DISR) provides multiplexing

of eQADC trigger sources, daisy chaining the DSPIs and external interrupt signal multiplexing.

MPC5553 Microcontroller Data Sheet, Rev. 0

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

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