CY7C1373CV25-100BGC datasheet, PDF

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CY7C1373CV25-100BGC: DescriptionZBT SRAM, 1MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119; Categorystorage; File Size723KB，31 Pages; ManufacturerCypress Semiconductor

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CY7C1373CV25-100BGC Overview

ZBT SRAM, 1MX18, 8.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119

CY7C1373CV25-100BGC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	BGA
package instruction	14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
Contacts	119
Reach Compliance Code	not_compliant
ECCN code	3A991.B.2.A
Is Samacsys	N
Maximum access time	8.5 ns
Other features	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	100 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	18874368 bit
Memory IC Type	ZBT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA119,7X17,50
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	220
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	2.4 mm
Maximum standby current	0.07 A
Minimum standby current	2.38 V
Maximum slew rate	0.175 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm
Base Number Matches	1

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CY7C1371CV25

CY7C1373CV25

18-Mb (512K x 36/1M x 18) Flow-through

SRAM with NoBL™ Architecture

Features

•

No Bus Latency (NoBL) architecture eliminates

dead cycles between write and read cycles.

• Can support up to 133-MHz bus operations with zero

wait states

• Data is transferred on every clock

•

Pin compatible and functionally equivalent to ZBT

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

• Single 2.5V power supply

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 7.5 ns (for 117-MHz device)

— 8.5 ns (for 100-MHz device)

• Clock Enable to enable clock and suspend operation

• Synchronous self-timed writes

• Offered in JEDEC-standard 100 TQFP, 119-Ball BGA and

165-Ball fBGA packages

• Three chip enables for simple depth expansion

Functional Description

[1]

The CY7C1371CV25 is a 2.5V, 512K x 36/ 1M x 18

Synchronous Flow-through Burst SRAM designed specifically

to support unlimited true back-to-back Read/Write operations

without the insertion of wait states. The CY7C1371CV25 is

equipped with the advanced No Bus Latency (NoBL) logic

required to enable consecutive Read/Write operations with

data being transferred on every clock cycle. This feature

dramatically improves the throughput of data through the

SRAM, especially in systems that require frequent Write-Read

transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

Write operations are controlled by the two or four Byte Write

Select (BW

) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE

, CE

) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Selection Guide

133 MHz

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

6.5

210

117 MHz

7.5

190

100 MHz

8.5

175

Unit

Notes:

1. For best–practices recommendations, please refer to the Cypress application note

System Design Guidelines

on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05236 Rev. *B

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised February 26, 2004

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