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PPC405CR-3BC266C: DescriptionPowerPC 405CR Embedded Processor; File Size436KB，42 Pages; Manufactureramcc [applied micro circuits corp]

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PPC405CR-3BC266C Overview

PowerPC 405CR Embedded Processor

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Part Number PPC405CR

Revision 1.02 – January 11, 2005

PPC405CR

Features

•

Data Sheet

PowerPC 405CR Embedded Processor

PowerPC

405 32-bit RISC processor core

operating up to 266MHz

- Memory Management Unit

- 16KB instruction and 8KB data caches

- Multiply-Accumulate (MAC) function,

including fast multiply unit

- Programmable Timers

Synchronous DRAM (SDRAM) interface oper-

ating up to 133MHz

- 32-bit interface for non-ECC applications

- 40-bit interface serves 32 bits of data plus 8

check bits for ECC applications

External Peripheral Bus

- Flash ROM/Boot ROM interface

- Direct support for 8-, 16-, or 32-bit SRAM and

external peripherals

- Up to eight devices

- External Mastering supported

•

DMA support for external peripherals, internal

UART and memory

- Scatter-gather chaining supported

- Four channels

Programmable Interrupt Controller supports

interrupts from a variety of sources

- Supports 7 external and 10 internal interrupts

- Edge triggered or level-sensitive

- Positive or negative active

- Non-critical or critical interrupt to processor

core

- Programmable critical interrupt priority

ordering

Two serial ports (16550 compatible UART)

One IIC interface

General Purpose I/O (GPIO) available

Supports JTAG for board level testing

Internal Processor Local Bus (PLB) runs at

SDRAM interface frequency

•

Description

The PowerPC 405CR (PPC405CR) is a 32-bit RISC

embedded controller. High performance, peripheral

integration, and low cost make the device ideal for

wired communications, network printers, and other

computing applications.

This device is an easy upgrade for systems based on

PowerPC 403xx embedded processors, while provid-

ing a base for custom chip designs.

The controller is powered by a PPC405 embedded

core. This core tightly couples a 266 MHz CPU, MMU,

instruction and data caches, and debug logic. Fine-

tuning of the core reduces data transfer overhead,

minimizes pipeline stalls, and improves performance.

The PPC405CR employs the IBM CoreConnect

™

bus

architecture. This architecture, as implemented on the

PPC405CR, consists of a 64-bit, 133-MHz Processor

Local Bus (PLB) and a 32-bit, 66-MHz On-Chip

Peripheral Bus (OPB). High-performance peripherals

attach to the PLB and less performance-critical periph-

erals attach to the OPB.

Technology: CMOS SA-12E 0.25

µm

(0.18

µm

eff

)

Package: 27 mm, 316-ball enhanced plastic ball grid

array (E-PBGA)

Power (estimated): Typical 0.8 W, Maximum 2.0 W at

200MHz.

AMCC

PPC405CR – PowerPC 405CR Embedded Processor

Revision 1.02 – January 11, 2005

Data Sheet

Contents

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering, PVR, and JTAG Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Address Map Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Intialization Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pull-Up and Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Unused I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

External Bus Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

AMCC

PPC405CR – PowerPC 405CR Embedded Processor

Revision 1.02 – January 11, 2005

Data Sheet

List of Figures

Figure 1. PPC405CR Embedded Controller Functional Block Diagram .................................................................. 5

Figure 2. 27mm, 316-Ball E-PBGA Package ......................................................................................................... 10

Figure 3. Package Thermal Specifications ............................................................................................................ 28

Figure 4. 5V-Tolerant I/O Input Current ................................................................................................................. 30

Figure 5. Timing Waveform .................................................................................................................................... 32

Figure 6. Input Setup and Hold Waveform ............................................................................................................. 35

Figure 7. Output Delay and Float Timing Waveform .............................................................................................. 35

List of Tables

Table 1. System Memory Address Map 4GB System Memory ................................................................................ 6

Table 2. DCR Address Map 4KB Device Configuration Register ............................................................................. 6

Table 3. Signals Listed Alphabetically ................................................................................................................... 11

Table 4. Signals Listed by Ball Assignment ........................................................................................................... 18

Table 5. Pin Summary ........................................................................................................................................... 21

Table 6. Signal Functional Description .................................................................................................................. 23

Table 7. Absolute Maximum Ratings ..................................................................................................................... 28

Table 8. Recommended DC Operating Conditions ................................................................................................ 29

Table 9. Input Capacitance .................................................................................................................................... 30

Table 10. Clocking Specifications .......................................................................................................................... 32

Table 11. Peripheral Interface Clock Timings ........................................................................................................ 34

Table 12. I/O Specifications—All speeds ............................................................................................................... 36

Table 13. I/O Specifications—133 and 200MHz .................................................................................................... 37

Table 14. I/O Specifications—266MHz .................................................................................................................. 38

Table 15. Strapping Pin Assignments .................................................................................................................... 39

AMCC

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