GAL20V8A-15NI datasheet, PDF - EEWORLD Datasheet

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GAL20V8A-15NI: DescriptionEE PLD, 15ns, PDIP24, PLASTIC, DIP-24; CategoryProgrammable logic Programmable logic devices; File Size272KB，4 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/

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GAL20V8A-15NI Overview

EE PLD, 15ns, PDIP24, PLASTIC, DIP-24

GAL20V8A-15NI Parametric

Parameter Name	Attribute value
Maker	Texas Instruments
package instruction	DIP,
Reach Compliance Code	unknown
Is Samacsys	N
Other features	POWER-UP RESET; REGISTER PRELOAD
maximum clock frequency	41.6 MHz
JESD-30 code	R-PDIP-T24
length	31.915 mm
Dedicated input times	12
Number of I/O lines	8
Number of terminals	24
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	12 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Programmable logic type	EE PLD
propagation delay	15 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	7.62 mm
Base Number Matches	1

GAL20V8A-15NI Related Products

	GAL20V8A-15NI	GAL20V8A-12NC	GAL20V8A-20VI	GAL20V8A-15NC	GAL20V8A-15VI
Description	EE PLD, 15ns, PDIP24, PLASTIC, DIP-24	EE PLD, 12ns, PDIP24, PLASTIC, DIP-24	EE PLD, 20ns, PQCC28, PLASTIC, LCC-28	EE PLD, 15ns, PDIP24, PLASTIC, DIP-24	EE PLD, 15ns, PQCC28, PLASTIC, LCC-28
Maker	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments
package instruction	DIP,	DIP,	QCCJ,	DIP,	QCCJ,
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown
Is Samacsys	N	N	N	N	N
Other features	POWER-UP RESET; REGISTER PRELOAD	POWER-UP RESET; REGISTER PRELOAD	POWER-UP RESET; REGISTER PRELOAD	POWER-UP RESET; REGISTER PRELOAD	POWER-UP RESET; REGISTER PRELOAD
maximum clock frequency	41.6 MHz	45.5 MHz	33.3 MHz	41.6 MHz	41.6 MHz
JESD-30 code	R-PDIP-T24	R-PDIP-T24	S-PQCC-J28	R-PDIP-T24	S-PQCC-J28
length	31.915 mm	31.915 mm	11.43 mm	31.915 mm	11.43 mm
Dedicated input times	12	12	12	12	12
Number of I/O lines	8	8	8	8	8
Number of terminals	24	24	28	24	28
Maximum operating temperature	85 °C	75 °C	85 °C	75 °C	85 °C
Minimum operating temperature	-40 °C	-	-40 °C	-	-40 °C
organize	12 DEDICATED INPUTS, 8 I/O	12 DEDICATED INPUTS, 8 I/O	12 DEDICATED INPUTS, 8 I/O	12 DEDICATED INPUTS, 8 I/O	12 DEDICATED INPUTS, 8 I/O
Output function	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	DIP	DIP	QCCJ	DIP	QCCJ
Package shape	RECTANGULAR	RECTANGULAR	SQUARE	RECTANGULAR	SQUARE
Package form	IN-LINE	IN-LINE	CHIP CARRIER	IN-LINE	CHIP CARRIER
Programmable logic type	EE PLD	EE PLD	EE PLD	EE PLD	EE PLD
propagation delay	15 ns	12 ns	20 ns	15 ns	15 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	5.08 mm	4.57 mm	5.08 mm	4.57 mm
Maximum supply voltage	5.5 V	5.25 V	5.5 V	5.25 V	5.5 V
Minimum supply voltage	4.5 V	4.75 V	4.5 V	4.75 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	YES	NO	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL EXTENDED	INDUSTRIAL	COMMERCIAL EXTENDED	INDUSTRIAL
Terminal form	THROUGH-HOLE	THROUGH-HOLE	J BEND	THROUGH-HOLE	J BEND
Terminal pitch	2.54 mm	2.54 mm	1.27 mm	2.54 mm	1.27 mm
Terminal location	DUAL	DUAL	QUAD	DUAL	QUAD
width	7.62 mm	7.62 mm	11.43 mm	7.62 mm	11.43 mm
Base Number Matches	1	1	1	1	1

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