DECL-150 datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > logic> DECL-150

DECL-150: DescriptionActive Delay Line, 1-Func, 5-Tap, True Output, ECL, MODULE-16/9; Categorylogic; File Size30KB，1 Pages; ManufacturerRhombus Industries, Inc.; Websitehttp://www.rhombus-ind.com/

Download Datasheet Parametric Compare View All

DECL-150 Overview

Active Delay Line, 1-Func, 5-Tap, True Output, ECL, MODULE-16/9

DECL-150 Parametric

Parameter Name	Attribute value
Maker	Rhombus Industries, Inc.
Parts packaging code	DIP
package instruction	DIP,
Contacts	9
Reach Compliance Code	unknown
Is Samacsys	N
Other features	MAX RISE TIME CAPTURED
series	10K
JESD-30 code	R-XDIP-T9
Logic integrated circuit type	ACTIVE DELAY LINE
Number of functions	1
Number of taps/steps	5
Number of terminals	9
Maximum operating temperature	85 °C
Minimum operating temperature	-30 °C
Output polarity	TRUE
Package body material	UNSPECIFIED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Maximum supply current (ICC)	75 mA
programmable delay line	NO
Certification status	Not Qualified
Maximum seat height	7.62 mm
surface mount	NO
technology	ECL
Temperature level	OTHER
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Total delay nominal (td)	150 ns
width	7.62 mm
Base Number Matches	1

Preview

Download Datasheet

View All

10K ECL Logic Buffered Delay 16-Pin Modules

5-Tap: DECL • Single: FECL • Triple: MECL

Electrical Specifications at 25

Delay

Single

Triple

(ns)

10K P/N

FECL-3

MECL-3

3 ± 0.5

FECL-4

MECL-4

4 ± 0.5

FECL-5

MECL-5

5 ± 0.5

FECL-6

MECL-6

6 ± 0.75

FECL-7

MECL-7

7 ± 0.75

FECL-8

MECL-8

8 ± 0.8

FECL-9

MECL-9

9 ± 1.0

FECL-10

MECL-10

10 ± 1.0

FECL-15

MECL-15

15 ± 1.5

FECL-20

MECL-20

20 ± 1.5

FECL-25

MECL-25

25 ± 1.5

FECL-50

MECL-50

50 ± 2.5

FECL-60

----

60 ± 3.0

FECL-75

----

75 ± 3.75

FECL-100

----

100 ± 5.0

Electrical Specifications at 25

Tap Delay Tolerances +/- 5% or 1.5ns (+/- 0.8ns <10ns)

10K ECL

5 Tap P/N

Tap 1

Tap 2

Tap 3

Tap 4

Total - Tap 5

DECL-6

DECL-10

DECL-15

DECL-20

DECL-25

DECL-30

DECL-40

DECL-45

DECL-50

DECL-75

DECL-100

DECL-125

DECL-150

DECL-200

DECL-250

2.0

3.0

4.0

5.0

6.0

8.0

9.0

10.0

15.0

20.0

25.0

30.0

40.0

50.0

3.0

4.0

6.0

8.0

10.0

12.0

16.0

18.0

20.0

30.0

40.0

50.0

60.0

80.0

100.0

4.0

6.0

9.0

12.0

15.0

18.0

24.0

27.0

30.0

45.0

60.0

75.0

90.0

120.0

150.0

5.0

8.0

12.0

16.0

20.0

24.0

32.0

36.0

40.0

60.0

80.0

100.0

120.0

160.0

200.0

6 ± 0.8

10 ± 1.0

15 ± 1.5

20 ± 1.5

25 ± 1.5

30 ± 1.5

40 ± 2.0

45 ± 2.25

50 ± 2.5

75 ± 3.75

100 ± 5.0

125 ± 6.25

150 ± 7.5

200 ± 10.0

250 ± 12.5

Tap-to-Tap

(ns)

∗∗ 1 ± 0.4

2 ± 0.6

3 ± 0.8

4 ± 1.0

5 ± 1.0

6 ± 1.5

8 ± 2.0

9 ± 2.0

10 ± 2.0

15 ± 2.5

20 ± 3.0

25 ± 3.0

30 ± 3.0

40 ± 4.0

50 ± 5.0

** This part numbers does not have 5 equal taps.

Specified Tap-to-Tap Delays are referenced to Tap 1.

OPERATING SPECIFICATIONS (10K ECL)

Supply Voltage .............................................. -5.20

0.25 VDC

Supply Current, I

DECL

.......................... 60 mA typ., 75 mA max.

Supply Current, I

FECL

.......................... 40 mA typ., 65 mA max.

Supply Current, I

MECL

....................... 85 mA typ., 105 mA max.

Logic “1” Input:

................................................ -0.98 V min.

.................................................. 265

µA

max.

Logic “0” Input:

................................................. -1.63 V max.

.................................................. 0.5 mA max.

Logic “1” Voltage Out .............................................. -0.96 V min.

Logic “0” Voltage Out .............................................. -1.65V max.

Output Rise Time .................................................. < 3.00 ns typ.

Input Pulse Width, P

(DECL,FECL) ......... 40% of total delay, min.

Input Pulse Width, P

(MECL) ................ 100% of total delay, min.

Operating Temperature Range ................................... -30

to +85

Storage Temperature Range ..................................... -65

to +150

(Measurements made at 25

Supply Voltage ................................................................. -5.20VDC

Input Pulse Voltage ....................................................... -.80V to -1.80V

Input Pulse Rise Time ......................................................... 3.00ns max.

Input Pulse Period ....................................................... 4.0 x Total Delay

Input Pulse Duty Cycle .................................................................... 50%

Outputs terminated through 100

Ω

to -2.00 Vdc.

Dimensions in Inches (mm) -- Unused Leads Removed Per Schematic

.810

(20.57)

MAX.

.400

(10.16)

MAX.

DECL

Style Schematic

Vcc Tap1 Tap3 Tap5

Vcc

Vee

Tap2 Tap4

FECL

Style Schematic

Vcc

OUT

TEST CONDITIONS

Vcc

Vee

MECL

Style Schematic

Vcc OUT

OUT

.260 .300

(6.60) (7.62)

TYP. MAX.

.120

(3.05)

MIN.

.010

(0.25)

TYP.

.050

(1.27)

TYP.

.100

(2.54)

TYP.

.020

(0.51)

TYP.

.300

(7.62)

Vcc

Vee

6SHFLILFDWLRQV VXEMHFW WR FKDQJH ZLWKRXW QRWLFH

www.rhombus-ind.com

UKRPEXV LQGXVWULHV LQF

Also Available in 10KH ECL Versions: DECLH, FECLH & MECLH Series

)RU RWKHU YDOXHV &XVWRP 'HVLJQV FRQWDFW IDFWRU\

sales@rhombus-ind.com

TEL: (714) 898-0960

FAX: (714) 896-0971

DECL_FM 2001-01

DECL-150 Related Products

	DECL-150	DECL-40	DECL-100	DECL-125	DECL-15	DECL-6	DECL-75	DECL-250	DECL-25	DECL-30
Description	Active Delay Line, 1-Func, 5-Tap, True Output, ECL, MODULE-16/9	Active Delay Line, 1-Func, 5-Tap, True Output, ECL, MODULE-16/9	Active Delay Line, 1-Func, 5-Tap, True Output, ECL, MODULE-16/9	Active Delay Line, 1-Func, 5-Tap, True Output, ECL, MODULE-16/9	Active Delay Line, 1-Func, 5-Tap, True Output, ECL, MODULE-16/9	Active Delay Line, 1-Func, 5-Tap, True Output, ECL, MODULE-16/9	Active Delay Line, 1-Func, 5-Tap, True Output, ECL, MODULE-16/9	Active Delay Line, 1-Func, 5-Tap, True Output, ECL, MODULE-16/9	Active Delay Line, 1-Func, 5-Tap, True Output, ECL, MODULE-16/9	Active Delay Line, 1-Func, 5-Tap, True Output, ECL, MODULE-16/9
Parts packaging code	DIP	DIP	DIP	DIP	DIP	DIP	DIP	DIP	DIP	DIP
package instruction	DIP,	MODULE-16/9	DIP,	DIP,	DIP,	DIP,	DIP,	DIP,	DIP,	DIP,
Contacts	9	9	9	9	9	9	9	9	9	9
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
Other features	MAX RISE TIME CAPTURED	MAX RISE TIME CAPTURED	MAX RISE TIME CAPTURED	MAX RISE TIME CAPTURED	MAX RISE TIME CAPTURED	MAX RISE TIME CAPTURED; INPUT TO 1ST TAP DELAY = 2NS	MAX RISE TIME CAPTURED	MAX RISE TIME CAPTURED	MAX RISE TIME CAPTURED	MAX RISE TIME CAPTURED
series	10K	10K	10K	10K	10K	10K	10K	10K	10K	10K
JESD-30 code	R-XDIP-T9	R-XDIP-T9	R-XDIP-T9	R-XDIP-T9	R-XDIP-T9	R-XDIP-T9	R-XDIP-T9	R-XDIP-T9	R-XDIP-T9	R-XDIP-T9
Logic integrated circuit type	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE	ACTIVE DELAY LINE
Number of functions	1	1	1	1	1	1	1	1	1	1
Number of taps/steps	5	5	5	5	5	5	5	5	5	5
Number of terminals	9	9	9	9	9	9	9	9	9	9
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-30 °C	-30 °C	-30 °C	-30 °C	-30 °C	-30 °C	-30 °C	-30 °C	-30 °C	-30 °C
Output polarity	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE	TRUE
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIP	DIP	DIP	DIP	DIP	DIP	DIP	DIP	DIP	DIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE	IN-LINE
Maximum supply current (ICC)	75 mA	75 mA	75 mA	75 mA	75 mA	75 mA	75 mA	75 mA	75 mA	75 mA
programmable delay line	NO	NO	NO	NO	NO	NO	NO	NO	NO	NO
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm
surface mount	NO	NO	NO	NO	NO	NO	NO	NO	NO	NO
technology	ECL	ECL	ECL	ECL	ECL	ECL	ECL	ECL	ECL	ECL
Temperature level	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Total delay nominal (td)	150 ns	40 ns	100 ns	125 ns	15 ns	6 ns	75 ns	250 ns	25 ns	30 ns
width	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm	7.62 mm
Base Number Matches	1	1	1	1	1	1	1	1	1	1
Maker	Rhombus Industries, Inc.	Rhombus Industries, Inc.	Rhombus Industries, Inc.	Rhombus Industries, Inc.	Rhombus Industries, Inc.	Rhombus Industries, Inc.	Rhombus Industries, Inc.	-	-	-
Is Samacsys	N	-	N	N	N	N	N	-	-	-

Recommended Resources

Single touch light switch circuit (2)

Liquid level controller circuit

New electronic ringer circuit diagram

555 burst audio circuit

Two-phase 2kHz audio oscillator

Computer motherboard circuit diagram 815 4_20

Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components