clocks. PhaseLink’s PL611s-18 offers the versatility
of using a single Crystal (MHz) or Reference Clock
input and producing up to two (kHz/MHz) system
clocks, or a combination of Reference and low
frequency outputs. The PL611s-18 is designed for
low-power applications with very stringent space
requirements and consumes ~1.0mA, while
producing 2 distinct outputs of 27MHz and 32kHz.
The power down feature of PL611s-18, when
activated, allows the IC to consume less than 5 A of
power.
The PL611s-18 fits in a small DFN, SC70, or SOT23
package. Cascading of the PL611s-18 with other
PhaseLink programmable clocks allow generating
system level clocking requirements, thereby
reducing the overall system implementation cost.
In addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(CLK0, F
REF
, F
REF
/2) output.
BLOCK DIAGRAM
XIN/FIN
XOUT
XTAL
OSC
Programmable
CLoad
F
REF
R-Counter
(5-bit)
M-Counter
(8-bit)
Phase
Detector
Charge
Pump
Loop
Filter
F
VCO
= F
REF
* (2 * M/R)
VCO
P-Counter
(14-bit)
F
OUT
= F
VCO
/ (2 * P)
Programmable Function
CLK
Programming
Logic
OE, PDB,
FSEL, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 2/23/07 Page 1
(Preliminary)
PL611s-18
0.5kHz-125MHz MHz to KHz Programmable Clock
T M
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
F
OUT
= F
REF
* M / (R * P)
Where M=8 bit
R= 5 bit
P= 14 bit
CLK0 = F
OUT
, F
REF
or F
REF
/ (2*P)
CLK1 = F
REF
, F
REF
/2, CLK0 or CLK0/2
Output Drive Strength
Three optional drive strengths to
choose from:
•
Low: 4mA
•
Std: 8mA (default)
•
High: 16mA
Programmable
Input/Output
One output pin can be configured as:
•
•
•
•
•
OE - input
FSEL - input
PDB – input
CLK1 – output
Programmable CLoad
PACKAGE PIN CONFIGURATION AND ASSIGNMENT
CLK0
CLK0
PL611s-18
PL611s-18
PL611s-18
PL611s-18
1
2
3
6
5
4
1
2
3
6
5
4
VDD
OE, PDB,
FSEL, CLK1
PL611s-18
VDD
OE, PDB,
FSEL, CLK1
PL611s-18
XIN/FIN
GND
CLK0
1
2
3
6
5
4
XOUT
OE,PDB,FSEL,CLK1
GND
XIN/FIN
GND
XIN/FIN
VDD
XOUT
XOUT
SOT23-
SOT23-6L
23
(3.0mmx3.0mmx1.35mm)
mmx3 mmx1 35mm
mm)
DFN-
DFN-6L
(2.0mmx1.3mmx0.6mm)
mmx1 mmx0 mm)
SC70-
SC70-6L
70
mmx1
(2.3mmx2.25mmx1.0mm)
mmx2 25mmx mm)
Name
XIN, FIN
GND
CLK0
VDD
Pin Assignment
DFN
SC70
SOT
Pin #
Pin#
Pin#
1
2
3
4
3
2
1
6
3
2
1
6
Type
I
P
O
P
Description
Crystal or Reference input pin.
GND connection
Programmable Clock Output
VDD connection
This programmable I/O pin can be configured as an Output
Enable (OE) input, Power Down input (PDB), Frequency Select
input (FSEL) or CLK1 output. This pin has an internal 60K
pull up resistor on OE, PDB and FSEL.
State
0
1 (default)
OE
Tri-state CLK
Operating mode
PDB
Power Down Mode
Operating mode
FSEL
Bank 0
Bank 1
OE, PDB,
FSEL, CLK1
5
5
5
I/O
XOUT
6
4
4
O
Crystal Output pin. Do Not Connect if FIN is used.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 2/23/07 Page 2
(Preliminary)
PL611s-18
0.5kHz-125MHz MHz to KHz Programmable Clock
T M
FUNCTIONAL DESCRIPTION
PL611s-18 is a highly featured, very flexible, advanced programmable PLL design for high performance, low-
power, small form-factor applications. The PL611s-18 accepts a crystal input of 10MHz to 50MHz or a reference
clock input of 1MHz to 125MHz and is capable of producing two outputs up to 125MHz. This flexible design allows
the PL611s-18 to deliver any PLL generated frequency, F
REF
(Crystal or Ref Clk) frequency or F
REF
/(2*P) to CLK0
and/or CLK1. Some of the design features of the PL611s-18 are mentioned below:
PLL Programming
The PLL in the PL611s-18 is fully programmable.
The PLL is equipped with an 5-bit input frequency
divider (R-Counter), and an 8-bit VCO frequency
feedback loop divider (M-Counter). The output of
the PLL is transferred to a 14-bit post VCO divider
(P-Counter). The output frequency is determined by
the following formula [F
OUT
= F
REF
* M / (R * P) ].
Clock Output (CLK0)
CLK0 is the main clock output. The PL611s-18 can
also be programmed to provide a second clock
output, CLK1, on the programmable I/O pin (see
OE/PDB/FSEL/CLK1 pin description below). The
output of CLK0 can be configured as the PLL output
(F
VCO
/(2*P)), F
REF
(Ref Clk Frequency) output, or
F
REF
/(2*P) output. The output drive level can be
programmed to Low Drive (4mA), Standard Drive
(8mA) or High Drive (16mA). The maximum output
frequency is 125MHz.
Clock Output (CLK1)
The CLK1 feature allows the PL611s-18 to have an
additional clock output. This output can be
programmed to one of the following:
F
REF
F
REF
/ 2
CLK0
CLK0 / 2
Output Enable (OE)
The Output Enable feature allows the user to enable
and disable the clock output(s) by toggling the OE
pin. The OE pin incorporates a 60k pull up resistor
giving a default condition of logic “1”. Pulling the OE
pin low “0” will tri-state the output buffers.
Power-Down Control (PDB)
The Power Down (PDB) feature allows the user to put
the PL611s-18 into “Sleep Mode”. When activated
(logic ‘0’), PDB ‘Disables the PLL, the oscillator
circuitry, counters, and all other active circuitry and
tri-state the output buffers. In Power Down mode the
IC consumes <5 A of power. The PDB pin
incorporates a 60k pull up resistor giving a default
condition of logic “1”.
Frequency Select (FSEL)
The Frequency Select (FSEL) feature allows the
PL611s-18 to switch between two pre-programmed
outputs allowing the device “On the Fly” frequency
switching. The FSEL pin incorporates a 60k pull up
resistor giving a default condition of logic “1”.
Programmable CLoad
The PL611s-18 is equipped with programmable S-
Caps to allow the Cload to be tuned from 8pF to
12pF.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 2/23/07 Page 3
(Preliminary)
PL611s-18
0.5kHz-125MHz MHz to KHz Programmable Clock
T M
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature (Green package)
Data Retention @ 85°C
Storage Temperature
Ambient Operating Temperature*
SYMBOL
V
DD
V
I
V
O
MIN.
MAX.
7
V
DD
+
0.5
V
DD
+
0.5
260
150
85
UNITS
V
V
V
°C
Year
°C
°C
-
0.5
-
0.5
-
0.5
10
T
S
-65
-40
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Crystal Input Frequency (XIN)
Input (FIN) Frequency
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Output Frequency
Settling Time
Output Enable Time
VDD Sensitivity
Output Rise Time
Output Fall Time
Duty Cycle
Period Jitter,Pk-to-Pk*
(measured from 10,000 samples)
* Note: Jitter performance depends
CONDITIONS
Fundamental Crystal
@ V
DD
=3.3V
@ V
DD
=2.5V
@ V
DD
=1.8V
Internally AC coupled (High Frequency)
Internally AC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ V
DD
=3.3V
@ V
DD
=2.5V
@ V
DD
=1.8V
At power-up (after V
DD
increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
Frequency vs. V
DD
+/-10%
15pF Load, 10/90% V
DD
, High Drive, 3.3V
15pF Load, 90/10% V
DD
, High Drive, 3.3V
V
DD
/2
With capacitive decoupling between VDD and
GND.
on the programming parameters.
MIN.
10
1
0.9
0.1
TYP.
MAX.
50
125
90
65
V
DD
V
DD
125
90
65
2
10
2
2
1.7
1.7
55
UNITS
MHz
MHz
Vpp
V
pp
MHz
MHz
MHz
ms
ns
ms
ppm
ns
ns
%
ps
-2
1.2
1.2
45
50
70
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 2/23/07 Page 4
(Preliminary)
PL611s-18
0.5kHz-125MHz MHz to KHz Programmable Clock
T M
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic, with
Loaded CMOS Outputs
Supply Current, Dynamic with
Loaded CMOS Outputs
PLL Off: Supply Current, Dynamic,
with Loaded CMOS Output
PLL Off: Supply Current, Dynamic,
with Loaded CMOS Output
PLL Off: Supply Current, Dynamic
with Loaded CMOS Output
PLL Off: Supply Current, Dynamic
with Loaded CMOS Output
Supply Current, Dynamic, with
Loaded Outputs
Operating Voltage
Output Low Voltage
Output High Voltage
Output Current, Low Drive
Output Current, Standard Drive
Output Current, High Drive
Short-Circuit Current
SYMBOL
I
DD
I
DD
I
DD
I
DD
I
DD
I
DD
I
DD
I
DD
V
DD
V
OL
V
OH
I
OSD
I
OSD
I
OHD
I
S
CONDITIONS
@ V
DD
=3.3V,
load=15pF
@ V
DD
=2.5V,
load=10pF
@ V
DD
=1.8V,
load=5pF
@ V
DD
=3.3V,
load=15pF
@ V
DD
=2.5V,
load=10pF
@ V
DD
=1.8V,
load=5pF
@ V
DD
=1.8V,
load=5pF
When PDB=0
27MHz,
27MHz,
27MHz,
27MHz,
27MHz,
27MHz,
32kHz,
MIN.
TYP.
4.0
2.7
0.9
2.0
1.3
0.8
0.2
MAX.
UNITS
mA
mA
mA
mA
mA
mA
mA
5
1.62
3.63
0.4
A
V
V
V
mA
mA
mA
I
OL
= +4mA Standard Drive
I
OH
= -4mA Standard Drive
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
OL
= 0.4V, V
OH
= 2.4V
V
DD
– 0.4
4
8
16
±50
mA
* Note: Please contact PhaseLink, if super-low-power is required.
CRYSTAL SPECIFICATIONS
PARAMETERS
Fundamental Crystal Resonator Frequency
Crystal Loading Rating
(The IC can be programmed for any value in this range.)
Maximum Sustainable Drive Level
Operating Drive Level
Shunt Capacitance
Metal Can Crystal
ESR Max
Shunt Capacitance
Small SMD Crystal
ESR Max
SYMBOL
F
XIN
C
L (xtal)
MIN.
10
8
TYP.
MAX.
50
12
100
UNITS
MHz
pF
µW
µW
pF
pF
30
C0
ESR
C0
ESR
5.5
50
2.5
80
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
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