A32200DX-2BG313C datasheet, PDF

Datasheet> All Categories > Programmable logic> A32200DX-2BG313C

A32200DX-2BG313C: DescriptionField Programmable Gate Array, 1230 CLBs, 20000 Gates, CMOS, PBGA313, BGA-313; CategoryProgrammable logic; File Size218KB，22 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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A32200DX-2BG313C Overview

Field Programmable Gate Array, 1230 CLBs, 20000 Gates, CMOS, PBGA313, BGA-313

A32200DX-2BG313C Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Actel
package instruction	BGA-313
Reach Compliance Code	compliant
Is Samacsys	N
JESD-30 code	S-PBGA-B313
JESD-609 code	e0
length	35 mm
Humidity sensitivity level	3
Configurable number of logic blocks	1230
Equivalent number of gates	20000
Number of terminals	313
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1230 CLBS, 20000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	IBGA
Package shape	SQUARE
Package form	GRID ARRAY, INTERSTITIAL PITCH
Peak Reflow Temperature (Celsius)	225
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	2.52 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	2.54 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	35 mm
Base Number Matches	1

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Pr eli m i nar y

3200DX Field Programmable Gate Arrays

– The System Logic Integrator

™

Family

Fe atur es

High Capacity

Ge ne r al D e s c r ip t i on

The 3200DX, the first device family in Actel’s Integrator™

Series, are the first FPGAs optimized for high-speed,

high-complexity system logic integration. Based on Actel’s

proprietary PLICE antifuse technology and state-of-the-art

0.6-micron double metal CMOS process, the 3200DX offers

a fine-grained, register-rich architecture with the industry’s

fastest embedded dual-port SRAM.

The 3200DX was designed to integrate high performance

system logic functions typically implemented in multiple

CPLDs, PALs, and FPGAs. The 3200DX is the first

programmable logic device to embed dual-port SRAM into

the programmable array. Offering 5 ns access time, the

3200DX provides the fastest embedded SRAM of any

programmable logic device on the market today. This

combination of fast, flexible SRAM blocks with a true

dual-port architecture, allows designers to implement

extremely fast SRAM functions such as FIFOs, LIFOs and

scratchpad memory. The large number of storage elements

can efficiently address applications requiring wide datapath

manipulation and transformation functions such as

telecommunications, networking, DSP and bus interfaces.

The control and decode functions typically implemented in

CPLDs can easily be integrated into the 3200DX by taking

advantage of the wide decode modules.

The 3200DX family is supported by Actel’s Designer Series

3.0 software which provides a seamless integration into any

ASIC design flow. The Designer Series development tools

offer automatic or fixed pin assignments, automatic

placement and routing (with optional manual placement),

•

Up to 40,000 logic gates

Up to 4 Kbits dual-port SRAM

Fast wide decode circuitry

Up to 292 User-programmable I/O Pins

200 MHz datapath applications

5 ns Dual-Port SRAM

100 MHz FIFOs

7.5 ns 35-bit Address Decode

High Performance

Ease-of-Integration

• JTAG 1149.1 Boundary Scan Testing

• Synthesis-friendly architecture supports ASIC design

methodologies

• 95–100% logic utilization using automatic Place and

Route Tools

• Deterministic, user-controllable timing via

DirectTime

™

software tools

• Designer Series

™

development tool support including

interfaces to popular design environments such as

Cadence, Escalade, Exemplar Logic, IST, Mentor

Graphics, Synopsys and Viewlogic

• Pin compatible with 1200XL Family

Prod uct Fami ly P rof il e

Device

Capacity

Logic Gates

Dual-Port SRAM Bits

Logic Modules

Sequential

Combinatorial

Decode

SRAM Modules (64x4 or 32x8)

Clocks

JTAG

User I/O

A3265DX

6,500

N/A

510

475

N/A

126

A32100DX

10,000

2,048

700

662

Yes

156

A32140DX

14,000

N/A

954

912

N/A

Yes

176

A32200DX

20,000

2,560

1,230

1,184

Yes

206

A32300DX

30,000

3,072

1,888

1,833

Yes

254

A32400DX

40,000

4,096

2,526

2,466

Yes

292

A u g us t 1 9 9 5

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