MC74VHC08MR2 datasheet, PDF - EEWORLD Datasheet

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MC74VHC08MR2: DescriptionAHC/VHC SERIES, QUAD 2-INPUT AND GATE, PDSO14, EIAJ, SOIC-14; Categorylogic; File Size134KB，7 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn

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MC74VHC08MR2 Overview

AHC/VHC SERIES, QUAD 2-INPUT AND GATE, PDSO14, EIAJ, SOIC-14

MC74VHC08MR2 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ON Semiconductor
Parts packaging code	SOIC
package instruction	EIAJ, SOIC-14
Contacts	14
Reach Compliance Code	compliant
Is Samacsys	N
series	AHC/VHC
JESD-30 code	R-PDSO-G14
JESD-609 code	e0
length	10.2 mm
Logic integrated circuit type	AND GATE
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	225
propagation delay (tpd)	14 ns
Certification status	Not Qualified
Maximum seat height	2.05 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	5.275 mm
Base Number Matches	1

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MC74VHC08

Quad 2-Input AND Gate

The MC74VHC08 is an advanced high speed CMOS 2−input AND

gate fabricated with silicon gate CMOS technology. It achieves high

speed operation similar to equivalent Bipolar Schottky TTL while

maintaining CMOS low power dissipation.

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output. The

inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V

systems to 3.0 V systems.

Features

http://onsemi.com

MARKING

DIAGRAMS

SOIC−14

D SUFFIX

CASE 751A

VHC08G

AWLYWW

•

High Speed: t

= 4.3 ns (Typ) at V

= 5.0 V

Low Power Dissipation: I

= 2.0

(Max) at T

= 25°C

High Noise Immunity: V

NIH

= V

NIL

= 28% V

Power Down Protection Provided on Inputs

Balanced Propagation Delays

Designed for 2.0 V to 5.5 V Operating Range

Low Noise: V

OLP

= 0.8 V (Max)

Pin and Function Compatible with Other Standard Logic Families

Latchup Performance Exceeds 300 mA

ESD Performance:

Human Body Model > 2000 V;

Machine Model > 200 V

•

Chip Complexity: 24 FETs or 6 Equivalent Gates

•

These Devices are Pb−Free and are RoHS Compliant

Y = AB

TSSOP

DT SUFFIX

CASE 948G

74VHC08

ALYWG

VHC

ALYW

SOEIAJ−14

M SUFFIX

CASE 965

WL, L

WW, W

G or

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

Figure 1. Logic Diagram

GND

(Top View)

FUNCTION TABLE

Inputs

Output

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

Figure 2. Pinout: 14−Lead Packages

Semiconductor Components Industries, LLC, 2011

May, 2011

−

Rev. 8

Publication Order Number:

MC74VHC08/D

MC74VHC08MR2 Related Products

	MC74VHC08MR2	MC74VHC08DTG	MC74VHC08DR	MC74VHC08DTRG	MC74VHC08DTR
Description	AHC/VHC SERIES, QUAD 2-INPUT AND GATE, PDSO14, EIAJ, SOIC-14	AHC/VHC SERIES, QUAD 2-INPUT AND GATE, PDSO14, LEAD FREE, TSSOP-14	IC AHC/VHC SERIES, QUAD 2-INPUT AND GATE, PDSO14, SOIC-14, Gate	IC AHC/VHC SERIES, QUAD 2-INPUT AND GATE, PDSO14, LEAD FREE, TSSOP-14, Gate	IC AHC/VHC SERIES, QUAD 2-INPUT AND GATE, PDSO14, TSSOP-14, Gate
Is it Rohs certified?	incompatible	conform to	incompatible	conform to	incompatible
Maker	ON Semiconductor	ON Semiconductor	ON Semiconductor	ON Semiconductor	ON Semiconductor
Parts packaging code	SOIC	TSSOP	SOIC	TSSOP	TSSOP
package instruction	EIAJ, SOIC-14	TSSOP, TSSOP14,.25	SOP,	TSSOP, TSSOP14,.25	TSSOP, TSSOP14,.25
Contacts	14	14	14	14	14
Reach Compliance Code	compliant	compliant	compliant	compliant	not_compliant
series	AHC/VHC	AHC/VHC	AHC/VHC	AHC/VHC	AHC/VHC
JESD-30 code	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14	R-PDSO-G14
length	10.2 mm	5 mm	8.65 mm	5 mm	5 mm
Logic integrated circuit type	AND GATE	AND GATE	AND GATE	AND GATE	AND GATE
Number of functions	4	4	4	4	4
Number of entries	2	2	2	2	2
Number of terminals	14	14	14	14	14
Maximum operating temperature	85 °C	85 °C	85 °C	85 °C	85 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SOP	TSSOP	SOP	TSSOP	TSSOP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
propagation delay (tpd)	14 ns	14 ns	14 ns	14 ns	14 ns
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	2.05 mm	1.2 mm	1.75 mm	1.2 mm	1.2 mm
Maximum supply voltage (Vsup)	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	2 V	2 V	2 V	2 V	2 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.65 mm	1.27 mm	0.65 mm	0.65 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL
width	5.275 mm	4.4 mm	3.9 mm	4.4 mm	4.4 mm
JESD-609 code	e0	-	e0	-	e0
Peak Reflow Temperature (Celsius)	225	-	240	-	NOT SPECIFIED
Terminal surface	TIN LEAD	-	TIN LEAD	-	Tin/Lead (Sn/Pb)
Maximum time at peak reflow temperature	NOT SPECIFIED	-	30	-	NOT SPECIFIED
Load capacitance (CL)	-	50 pF	-	50 pF	50 pF
MaximumI(ol)	-	0.008 A	-	0.008 A	0.008 A
Encapsulate equivalent code	-	TSSOP14,.25	-	TSSOP14,.25	TSSOP14,.25
method of packing	-	RAIL	-	TAPE AND REEL	TAPE AND REEL
power supply	-	2/5.5 V	-	2/5.5 V	2/5.5 V
Prop。Delay @ Nom-Sup	-	9 ns	-	9 ns	9 ns
Schmitt trigger	-	NO	-	NO	NO

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