PIC18LF45J10-E/SP datasheet, PDF

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PIC18LF45J10-E/SP: Description8-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size177KB，6 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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PIC18LF45J10-E/SP Overview

8-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP44

PIC18LF45J10-E/SP Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microchip
Parts packaging code	DIP
package instruction	0.300 INCH, PLASTIC, DIP-28
Contacts	28
Reach Compliance Code	compli
ECCN code	3A991.A.2
Has ADC	YES
Address bus width
bit size	8
maximum clock frequency	40 MHz
DAC channel	NO
DMA channel	NO
External data bus width
JESD-30 code	R-PDIP-T28
JESD-609 code	e3
length	34.67 mm
Number of I/O lines	32
Number of terminals	28
On-chip program ROM width	16
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
RAM (bytes)	1024
rom(word)	16384
ROM programmability	FLASH
Maximum seat height	5.08 mm
speed	40 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	2 V
Nominal supply voltage	2.5 V
surface mount	NO
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Matte Tin (Sn)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER, RISC

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PIC18F24J10/25J10/44J10/45J10

PIC18F24J10/25J10/44J10/45J10 Rev. A2 Silicon Errata

The PIC18F24J10/25J10/44J10/45J10 Rev. A2 parts

you have received conform functionally to the Device

Data Sheet (DS39682A), except for the anomalies

described below. Any Data Sheet Clarification issues

related to the PIC18F24J10/25J10/44J10/45J10 will be

reported in a separate Data Sheet errata. Please check

the Microchip web site for any existing issues.

The following silicon errata apply only to

PIC18F24J10/25J10/44J10/45J10 devices with these

Device/Revision IDs:

Part Number

PIC18F24J10

PIC18LF24J10

PIC18F25J10

PIC18LF25J10

PIC18F44J10

PIC18LF44J10

PIC18F45J10

PIC18LF45J10

Device ID

0001 1101 000

0001 1101 010

0001 1100 000

0001 1100 010

0001 1101 001

0001 1101 011

0001 1100 001

0001 1100 011

Revision ID

0001

2. Module: EUSART

In asynchronous duplex communication, the

reception can get corrupted if any bit of the TXSTA

Work around

The CSRC (TXSTA<7>) bit should not be set.

Though this is a “don’t care” bit in Asynchronous

mode, make sure that this bit is not set.

3. Module: EUSART

In Synchronous mode, EUSART baud rates using

SPBRG values of ‘0’ and ‘1’ may not function

correctly.

Work around

Use another baud rate configuration to generate

the desired baud rate.

4. Module: EUSART

After the last received byte has been read from the

EUSART receive buffer, RCREG, the value is no

longer valid for subsequent read operations. The

RCREG register should only be read once for each

byte received.

Work around

After each byte is received from the EUSART,

store the byte into a user variable. To determine

when a byte is available to read from RCREG, poll

the RCIDL (BAUDCON<6>) bit for a low-to-high

transition, or use the EUSART Receive Interrupt

Flag, RCIF (PIR1<5>).

The Device IDs (DEVID1 and DEVID2) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in hexadecimal

in the format “DEVID2 DEVID1”.

1. Module: Timer1

In 16-Bit Asynchronous Counter mode or 16-Bit

Asynchronous Oscillator mode, the TMR1H buffer

does not update when TMR1L is read. This issue

only affects reading the TMR1H registers. The tim-

ers increment and set the interrupt flags as

expected. The Timer registers can also be written

as expected.

Work around

Use 8-bit mode by clearing the RD16 (T1CON<7>)

bit or use the synchronization option by clearing

T1SYNC (T1CON<2>).

5. Module: EUSART

In 9-Bit Asynchronous, Full-Duplex, Receive

mode, received data may be corrupted if the TX9D

bit (TXSTA<0>) is not modified immediately after

RCIDL (BAUDCON<6>) is set.

Work around

Only write to TX9D when a reception is not in

progress (RCIDL =

1).

No interrupt is associated

with RCIDL, therefore, it must be polled in software

to determine when TX9D can be updated.

2006 Microchip Technology Inc.

DS80269C-page 1

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