Ordering number : ENA0116A
LC863364C,LC863356C
LC863348C,LC863340C
LC863332C,LC863328C
LC863324C,LC863320C
LC863316C
Overview
CMOS IC
64K/56K/48K/40K/32K/28K/24K/20K/16K-byte ROM,
CGROM16K-byte
on-chip 640/512-byte RAM and 352×9-bit OSD RAM
8-bit 1-chip Microcontroller
The LC863364C/56C/48C/40C/32C/28C/24C/20C/16C are 8-bit single chip microcontrollers with the following on-chip
functional blocks:
•
CPU : Operable at a minimum bus cycle time of 0.424µs
•
On-chip ROM capacity
Program ROM : 64K/56K/48K/40K/32K/28K/24K/20K/16K bytes
CGROM : 16K bytes
•
On-chip RAM capacity : 640/512 bytes
•
OSD RAM : 352×9 bits
•
Five channels×8-bit AD Converter
•
Three channels×7-bit PWM
•
Two 16-bit timer/counters, 14-bit base timer
•
8-bit synchronous serial interface circuit
•
IIC-bus compliant serial interface circuit (Multi-master type)
•
ROM correction function
•
15-source 9-vectored interrupt system
•
Integrated system clock generator and display clock generator
X’tal oscillator (32.768kHz) for PLL reference is used for TV control
All of the above functions are fabricated on a single chip.
Note : This product includes the IIC bus interface circuit. If you intend to use the IIC bus interface, please notify us of this in
advance of our receiving your program ROM code order.
Purchase of SANYO IIC components conveys a license under the Philips IIC Patents Rights to use these components in
an IIC system, provided that the system conforms to the IIC Standard Specification as defined by Philips.
Trademarks
IIC is a trademark of Philips Corporation.
Ver.1.00
52506HKIM No.A0116-1/21
LC863364C/56C/48C/40C/32C/28C/24C/20C/16C
Features
Read-Only Memory (ROM) :
65536×8 bits / 57344×8 bits / 49152×8 bits /
40960×8 bits / 32768×8 bits / 28672×8 bits /
24576×8 bits / 20480×8 bits / 16384×8 bits for program
16128×8 bits for CGROM
512×8 bits (working area) : LC863364C/56C/48C/40C
384×8 bits (working area) : LC863332C/28C/24C/20C/16C
128×8 bits (working or ROM correction function)
352×9 bits (for CRT display)
Random Access Memory (RAM) :
OSD Functions
•
Screen display : 36 characters×16 lines (by software)
•
RAM
: 352 words (9 bits per word)
Display area : 36 words×8 lines
Control area : 8 words×8 lines
•
Characters
Up to 252 kinds of 16×32 dot character fonts (4 characters including 1 test character are not programmable)
Each font can be divided into two parts and used as two fonts: a 16×17 dot and 8×9 dot character font
•
Various character attributes
Character colors
: 16colors
Character background colors : 16colors
Fringe / shadow colors
: 16colors
Full screen colors
: 16colors
Rounding
Underline
Italic character (slanting)
•
Attribute can be changed without spacing
•
Vertical display start line number can be set for each row independently (Rows can be overlapped)
•
Horizontal display start position can be set for each row independently
•
Horizontal pitch (9 to 16 dots)*1 and vertical pitch (1 to 32 dots) can be set for each row independently
•
Different display modes can be set for each row independently
Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplified graphic mode
•
Ten character sizes *1
Horez.
×
Vert. = (1×1), (1×2), (2×2), (2×4), (0.5×0.5)
(1.5×1), (1.5×2), (3×2), (3×4), (0.75×0.5)
•
Shuttering and scrolling on each row
•
Simplified Graphic Display
Note *1: range depends on display mode : refer to the manual for details.
Bus Cycle Time / Instruction-Cycle Time
Bus Cycle Time
0.424µs
7.5µs
183.1µs
Instruction Cycle Time
0.848µs
15.0µs
366.2µs
System Clock Oscillation
Internal VCO
(Ref : X’tal 32.768kHz)
Internal RC
Crystal
800kHz
32.768kHz
4.5V to 5.5V
4.5V to 5.5V
Oscillation Frequency
14.156MHz
Voltage
4.5V to 5.5V
No.A0116-2/21
LC863364C/56C/48C/40C/32C/28C/24C/20C/16C
Ports
•
Input / Output Ports
: 5 ports (28 terminals)
Data direction programmable in nibble units
: 1 port (8 terminals)
(If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.)
Data direction programmable for each bit individually : 4 ports (20 terminals)
•
Input port
: 1 port (1 terminal)
AD Converter
•
5 channels×8-bit AD converters
Serial Interfaces
•
IIC-bus compliant serial interface (Multi-master type)
Consists of a single built-in circuit with two I/O channels. The two data lines and two clock lines can be connected
internally.
•
Synchronous 8-bit serial interface
PWM Output
•
3 channels×7-bit PWM
Timer
•
Timer 0 : 16-bit timer/counter
With 2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with a programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
The resolution of timer is 1 tCYC.
•
Timer 1 : 16-bit timer/PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable bit PWM (9 to 16 bits)
In mode0/1, the resolution of Timer1/PWM is 1 tCYC
In mode2/3, the resolution is selectable by program; tCYC or 1/2 tCYC
•
Base timer
Generate every 500ms overflow for a clock application
(using 32.768kHz crystal oscillation for the base timer clock)
Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow
(using 32.768kHz crystal oscillation for the base timer clock)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0
Remote Control Receiver Circuit (connected to the P73/INT3/T0IN terminal)
•
Noise rejection function
•
Polarity switching
Watchdog Timer
External RC circuit is required
Interrupt or system reset is activated when the timer overflows
ROM Correction Function
Max 128 bytes / 2 addresses
No.A0116-3/21
LC863364C/56C/48C/40C/32C/28C/24C/20C/16C
Interrupts
•
15 sources 9 vectored interrupts
1. External Interrupt INT0
2. External Interrupt INT1
3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits)
4. External Interrupt INT3, base timer
5. Timer/counter T0H (Upper 8 bits)
6. Timer T1H,T1L
7. SIO0
8. Vertical synchronous signal interrupt (VS), horizontal line (HS), AD
9. IIC, Port 0
•
Interrupt priority control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high
priority can be assigned to the interrupts from 3 to 9 listed above. For the external interrupt INT0 and INT1, low or
highest priority can be set.
Sub-routine Stack Level
•
A maximum of 128 levels (stack is built in the internal RAM)
Multiplication/division Instruction
•
16 bits×8 bits (7 instruction cycle times)
•
16 bits÷8 bits (7 instruction cycle times)
3 Oscillation Circuits
•
Built-in RC oscillation circuit used for the system clock
•
Built-in VCO circuit used for the system clock and OSD
•
X’tal oscillation circuit used for base timer, system clock and PLL reference
Standby Function
•
HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped.
This mode can be released by the interrupt request or the system reset.
•
HOLD mode
The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be
released by the following conditions.
- Pull the reset terminal (RES) to low level.
- Feed the selected level to either P70/INT0 or P71/INT1.
- Input the interrupt condition to Port 0.
Package
•
DIP42S (Lead-free type)
•
QIP48E (Lead-free type)
Development Tools
•
Flash EEPROM: LC86F3364A
•
Evaluation chip: LC863096
•
Emulator:
EVA86000 (main) + ECB863200* or ECB863200A (evaluation chip board)
+ POD863300 (pod: DIP42S) or POD863301 (pod: QIP48E)
* This product is no longer available
No.A0116-4/21
LC863364C/56C/48C/40C/32C/28C/24C/20C/16C
Package Dimensions
unit : mm
3025C
37.7
42
22
0.95
3.8 5.1max
0.51min
(4.25)
1.78
0.48
(1.05)
SANYO : DIP42S(600mil)
Package Dimensions
unit : mm
3156A
17.2
36
37
25
24
0.8
14.0
14.0
48
1
1.0
(1.5)
(2.7)
13
12
0.35
0.15
3.0max
0.1
SANYO : QIP48E(14X14)
17.2
0.25
1
21
15.24
13.8
No.A0116-5/21
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