PIC18F1230/1330
PIC18F1230/1330 Rev. A4 Silicon Errata
The PIC18F1230/1330 Rev. A4 parts you have
received conform functionally to the Device Data Sheet
(DS39758C), except for the anomalies described
below. Any Data Sheet Clarification issues related to
the PIC18F1230/1330 will be reported in a separate
Data Sheet errata. Please check the Microchip web site
for any existing issues.
The following silicon errata apply only to
PIC18F1230/1330 devices with these Device/
Revision IDs:
Part Number
PIC18F1230
PIC18F1330
Device ID
0001 1110 000
0001 1110 001
Revision ID
0 0101
0 0101
2. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In Synchronous Slave Transmission mode, the
TRMT bit (TXSTA<1>) may not indicate when the
TSR register is empty.
Work around
Instead of polling the TRMT bit to determine the
status of the EUSART, poll the TXIF flag
(PIR1<4>) to determine when new data can be
written to the TXREG register.
Date Codes that pertain to this issue:
All engineering and production devices.
The Device IDs (DEVID1 and DEVID2) are located at
addresses 3FFFFEh:3FFFFFh in the device’s
configuration space. They are shown in binary in the
format “DEVID2 DEVID1”.
All of the issues listed here will be addressed in future
revisions of the PIC18F1230/1330 silicon.
3. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In rare situations, one or more extra bytes have
been observed in a packet transmitted by the
module operating in Asynchronous mode. The
actual data is not lost or corrupted – only extra
bytes are added. The extra bytes may be 0x00 or
0xFF.
This situation occurs when the contents of the
transmit buffer (TXREG) are transferred to the
TSR at the end of the Stop bit period at the same
time that firmware writes to TXREG.
Note that TXIF is set at the beginning of the Stop
bit period.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
1. Module: Comparator
The CMPxIF flag, which indicates when each
comparator has a switched state, cannot be
cleared immediately after reading CMCON. The
mismatch condition that sets CMPxIF persists for
1 T
CY
after reading/writing CMCON.
Work around
Insert a
NOP
instruction between reading/writing
CMCON and clearing the CMPxIF flag.
Date Codes that pertain to this issue:
All engineering and production devices.
©
2008 Microchip Technology Inc.
DS80308D-page 1
PIC18F1230/1330
4. Module: Comparator Voltage Reference
The comparator voltage reference module
(CV
REF
) does not offer the option of bypassing the
CV
REF
module.
The CV
REF
module offers the option of providing
the following inputs to the comparators:
• Scaled V
DD
• Scaled V
REF
• No reference (disabled)
Table 1 shows how the CVREN and CVRSS bits
are configured to enable the options.
5. Module: Enhanced Universal
Synchronous Asynchronous
Receiver Transmitter (EUSART)
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
RCSTA <7> =
0)
• The EUSART is re-enabled (RCSTA <7> =
1)
• A two-cycle instruction is executed
Work around
Add a 2 T
CY
delay after re-enabling the EUSART.
1.
2.
3.
4.
5.
Disable Receive Interrupts (RCIE bit,
PIE1<5> =
0).
Disable the EUSART (RCSTA <7> =
0).
Re-enable the EUSART (RCSTA <7> =
1).
Re-enable receive interrupts (PIE1<5> =
1).
(This is the first T
CY
delay.)
Execute a
NOP
instruction.
(This is the second T
CY
delay.)
Date Codes that pertain to this issue:
All engineering and production devices.
TABLE 1:
VOLTAGE REFERENCE
OUTPUT
Comparator
Reference
CVREN
CVRSS
CVRCON<7> CVRCON<4>
0
1
1
x
(don’t care) Disabled
0
1
CV
REF
uses AV
DD
CV
REF
uses V
REF
DS80308D-page 2
©
2008 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
•
•
•
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
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The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, K
EE
L
OQ
, K
EE
L
OQ
logo, MPLAB, PIC, PICmicro,
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Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
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ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
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32
logo, PowerCal, PowerInfo,
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© 2008, Microchip Technology Incorporated, Printed in the
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Printed on recycled paper.
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and India. The Company’s quality system processes and procedures
are for its PIC
®
MCUs and dsPIC
®
DSCs, K
EE
L
OQ
®
code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
©
2008 Microchip Technology Inc.
DS80308D-page 5
MCU
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