PIC12F510
Memory Programming Specification
This document includes the
programming specifications for the
following devices:
• PIC12F510
1.1
Hardware Requirements
The PIC12F510 requires one power supply for V
DD
(5.0V) and one for V
PP
(12V).
1.2
Program/Verify Mode
1.0
PROGRAMMING THE
PIC12F510
The PIC12F510 is programmed using a serial method.
The Serial mode will allow the PIC12F510 to be
programmed while in the user’s system. This allows for
increased design flexibility. This programming
specification applies to PIC12F510 devices in all
packages.
The Program/Verify mode for the PIC12F510 allows
programming of user program memory, user ID loca-
tions, backup OSCCAL location and the Configuration
Word.
Pin Diagrams
PDIP, SOIC, MSOP
V
DD
GP5/OSC1/CLKIN
GP4/OSC2
MCLR/V
PP
/GP3
1
2
3
4
8
7
6
5
V
SS
GP0/AN0/CIN+/ICSPDAT
GP1/AN1/CIN-/ICSPCLK
GP2/AN2/COUT//T0CKI
TABLE 1-1:
Pin Name
GP1
GP0
MCLR/V
PP
/GP3
V
DD
V
SS
PIN DESCRIPTIONS (DURING PROGRAMMING): PIC12F510
During Programming
Function
ICSPCLK
ICSPDAT
Program/Verify mode
V
DD
V
SS
Pin Type
I
I/O
P
(1)
P
P
Pin Description
Clock input – Schmitt Trigger input
Data input/output – Schmitt Trigger input
Program Mode Select
Power Supply
Ground
Legend:
I = Input, O = Output, P = Power
Note 1:
In the PIC12F510, the programming high voltage is internally generated. To activate the Program/Verify
mode, high voltage of I
IHH
current capability (see Table 6-1) needs to be applied to the MCLR input.
©
2007 Microchip Technology Inc.
PIC12F510
DS41257B-page 1
PIC12F510
2.0
2.1
MEMORY MAPPING
User Program Memory Map
FIGURE 2-1:
PIC12F510 PROGRAM
MEMORY MAP
On-chip User
Program
Memory (Page 0)
On-chip User
Program
Memory (Page 1)
Reset Vector
User ID Locations
Backup OSCCAL value
Reserved
43Fh
440h
Unimplemented
Configuration Word
7FEh
7FFh
000h
The user memory space extends from (0x000-0x3FF)
on the PIC12F510. In Program/Verify mode, the pro-
gram memory space extends from (0x000-0x7FF) for
the PIC12F510. The first half, (0x000-0x3FF), is user
program memory. The second half, (0x400-0x7FF), is
configuration memory. The PC will increment from
(0x000-0x3FF) then to 0x400, (not to 0x000).
In the configuration memory space, 0x400-0x43F are
physically implemented. However, only locations
0x400-0x403 are available. Other locations are
reserved.
User Memory
Space
1FFh
200h
3FEh
3FFh
400h
403h
404h
405h
2.2
User ID Locations
A user may store identification information (ID) in four
user ID locations. The user ID locations are mapped in
[0x400:0x403]. It is recommended that the user use
only the four Least Significant bits (LSb) of each user
ID location. The user ID locations read out normally,
even after code protection is enabled. It is recom-
mended that user ID locations are written as
‘xxxx
xxxx bbbb’
where
‘bbbb’
is user ID information.
The 12 bits may be programmed, but only the four LSbs
are displayed by MPLAB
®
IDE. The
xxxx’s
are “don’t
care” bits and are not read by MPLAB IDE.
2.4
Config Memory
Space
Oscillator Calibration Bits
2.3
Configuration Word
The oscillator calibration bits are stored at the Reset
vector as the operand of a
MOVLW
instruction. Program-
ming interfaces must allow users to program the
calibration bits themselves for custom trimming of the
INTOSC. Capability for programming the calibration
bits when programming the entire memory array must
also be maintained for backwards compatibility.
The Configuration Word is physically located at 0x7FF.
It is only available upon Program mode entry. Once an
Increment Address command is issued, the Configura-
tion Word is no longer accessible, regardless of the
address of the program counter.
Note:
By convention, the Configuration Word is
stored at the logical address location of
0xFFF within the hex file generated for the
PIC12F510. This logical address location
may not reflect the actual physical address
for the part itself. It is the responsibility of
the programming software to retrieve the
Configuration Word from the logical
address within the hex file and granulate
the address to the proper physical location
when programming.
2.5
Backup OSCCAL Value
The backup OSCCAL value, 0x404, is a factory location
where the OSCCAL value is stored during testing of the
INTOSC. This location is not erased during a standard
Bulk Erase, but is erased if the PC is moved into
configuration memory prior to invoking a Bulk Erase. If
this value is erased, it is the user’s responsibility to
rewrite it back to this location for future use.
DS41257B-page 2
©
2007 Microchip Technology Inc.
PIC12F510
3.0
3.1
COMMANDS AND
ALGORITHMS
Program/Verify Mode
3.1.2
SERIAL PROGRAM/VERIFY
OPERATION
The Program/Verify mode is entered by holding pins
ICSPCLK and ICSPDAT low while raising V
DD
pin from
V
IL
to V
DD
. Then raise V
PP
from V
IL
to V
IHH
. Once in
this mode, the user program memory and configuration
memory can be accessed and programmed in serial
fashion. Clock and data are Schmitt Trigger input in this
mode.
The sequence that enters the device into the Program-
ming/Verify mode places all other logic into the Reset
state (the MCLR pin was initially at V
IL
). This means
that all I/O are in the Reset state (high-impedance
inputs).
The ICSPCLK pin is used for clock input and the
ICSPDAT pin is used for data input/output during serial
operation. To input a command, the clock pin is cycled
six times. Each command bit is latched on the falling
edge of the clock with the LSb of the command being
input first. The data must adhere to the setup (T
SET
1)
and hold (T
HLD
1) times with respect to the falling edge
of the clock (see Table 6-1).
Commands that do not have data associated with them
are required to wait a minimum of T
DLY
2 measured
from the falling edge of the last command clock to the
rising edge of the next command clock (see Table 6-1).
Commands that do have data associated with them
(Read and Load) are also required to wait T
DLY
2
between the command and the data segment
measured from the falling edge of the last command
clock to the rising edge of the first data clock. The data
segment, consisting of 16 clock cycles, can begin after
this delay.
Note:
After every End Programming command,
a delay of T
DIS
is required.
3.1.1
PROGRAMMING
The programming sequence loads a word, programs,
verifies and finally increments the PC.
Program/Verify mode entry will set the address to
0x7FF. The Increment Address command will
increment the PC. The available commands are shown
in Table 3-1.
FIGURE 3-1:
ENTERING HIGH
VOLTAGE PROGRAM/
VERIFY MODE
T
PPDP
T
HLD
0
The first and last clock pulses during the data segment
correspond to the Start and Stop bits, respectively.
Input data is a “don’t care” during the Start and Stop
cycles. The 14 clock pulses between the Start and Stop
cycles clock the 14 bits of input/output data. Data is
transferred LSb first.
During Read commands, in which the data is output
from the PIC12F510, the ICSPDAT pin transitions from
the high-impedance input state to the low-impedance
output state at the rising edge of the second data clock
(first clock edge after the Start cycle). The ICSPDAT pin
returns to the high-impedance state at the rising edge
of the 16th data clock (first edge of the Stop cycle). See
Figure 3-3.
The commands that are available are described in
Table 3-1.
V
PP
V
DD
ICSPDAT
ICSPCLK
TABLE 3-1:
COMMAND MAPPING FOR PIC12F510
Command
Mapping (MSb … LSb)
x
x
x
x
x
x
x
x
x
x
x
x
0
0
0
1
1
1
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
1
Internally Timed
Externally Timed
Data
0,
data (14),
0
0,
data (14),
0
Load Data for Program Memory
Read Data from Program Memory
Increment Address
Begin Programming
End Programming
Bulk Erase Program Memory
©
2007 Microchip Technology Inc.
DS41257B-page 3
PIC12F510
3.1.2.1
Load Data For Program Memory
After receiving this command, the chip will load in a
14-bit “data word” when 16 cycles are applied, as
described previously. Because this is a 12-bit core, the
two MSbs of the data word are ignored. A timing
diagram for the Load Data command is shown in
Figure 3-1.
FIGURE 3-2:
LOAD DATA COMMAND (PROGRAM/VERIFY)
1
2
3
4
5
6
T
DLY
2
1
2
3
4
5
15
16
ICSPCLK
ICSPDAT
0
1
0
T
SET
1
T
HLD
1
0
x
x
strt_bit
LSb
T
SET
1
-+
T
HLD
1
MSb
stp_bit
T
DLY
1
3.1.2.2
Read Data From Program Memory
After receiving this command, the chip will transmit
data bits out of the program memory (user or
configuration) currently addressed, starting with the
second rising edge of the clock input. The data pin will
go into Output mode on the second rising clock edge,
and it will revert to Input mode (high-impedance) after
the 16th rising edge. Because this is a 12-bit core, the
two MSbs of the 14-bit word will be read as ‘0’s.
If the program memory is code-protected (CP =
0),
portions of the program memory will be read as zeros.
See
Section 5.0 “Code Protection”
for details.
FIGURE 3-3:
READ DATA FROM PROGRAM MEMORY COMMAND
T
DLY
2
1
2
3
4
5
6
1
2
3
T
DLY
3
1
0
4
5
15
16
ICSPCLK
ICSPDAT
0
T
SET
1
T
HLD
1
Input
1
0
x
x
strt_bit
T
DLY
1
MSb
stp_bit
LSb
Output
Input
DS41257B-page 4
©
2007 Microchip Technology Inc.
PIC12F510
3.1.2.3
Increment Address
The PC is incremented when this command is
received. A timing diagram of this command is shown
in Figure 3-4.
It is not possible to decrement the address counter. To
reset this counter, the user must either exit and re-enter
Program/Verify mode or increment the PC from 0x7FF
to 0x000.
FIGURE 3-4:
INCREMENT ADDRESS COMMAND
T
DLY
2
1
2
3
4
5
6
1
Next Command
2
ICSPCLK
ICSPDAT
0
1
1
T
SET
1
0
x
x
T
HLD
1
3.1.2.4
Begin Programming (Externally
Timed)
A Load command must be given before every Begin
Programming command. Programming will begin after
this command is received and decoded. Programming
requires (T
PROG
) time and is terminated using an End
Programming command. This command programs the
current location, no erase is performed.
FIGURE 3-5:
BEGIN PROGRAMMING (EXTERNALLY TIMED)
T
PROG
1
2
3
4
5
6
End Programming Command
1
2
ICSPCLK
ICSPDAT
0
0
0
T
SET
1
1
x
x
0
1
T
HLD
1
©
2007 Microchip Technology Inc.
DS41257B-page 5
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