BUK9728-55A
N-channel TrenchMOS™ logic level FET
M3D308
Rev. 02 — 10 June 2004
Product data
1. Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™
1
technology, featuring very low on-state resistance.
Product availability:
BUK9728-55A in SOT186A (TO-220F).
2. Features
s
s
s
s
TrenchMOS™ technology
Q101 compliant
150
°C
rated
Logic level compatible.
3. Applications
s
Automotive and general purpose power switching:
x
12 V and 24 V loads
x
Motors, lamps and solenoids.
4. Pinning information
Table 1:
Pin
1
2
3
mb
Pinning - SOT186A, simplified outline and symbol
Description
gate (g)
drain (d)
source (s)
mounting base;
isolated
1 2 3
MBK110
Simplified outline
mb
Symbol
d
g
mbb076
s
SOT186A (TO-220F)
1.
TrenchMOS is a trademark of Koninklijke Philips Electronics N.V.
Philips Semiconductors
BUK9728-55A
N-channel TrenchMOS™ logic level FET
5. Quick reference data
Table 2:
V
DS
I
D
P
tot
T
j
R
DSon
Quick reference data
Conditions
T
mb
= 25
°C;
V
GS
= 5 V
T
mb
= 25
°C
T
j
= 25
°C;
V
GS
= 5 V; I
D
= 15 A
T
j
= 25
°C;
V
GS
= 4.5 V; I
D
= 15 A
Typ
-
-
-
-
23
-
Max
55
22
26
150
28
30
Unit
V
A
W
°C
mΩ
mΩ
drain-source voltage (DC)
drain current (DC)
total power dissipation
junction temperature
drain-source on-state resistance
Symbol Parameter
6. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
V
GSM
I
D
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
non-repetitive gate-source voltage
drain current (DC)
t
p
≤
50
µs
T
mb
= 25
°C;
V
GS
= 5 V;
Figure 2
and
3
T
mb
= 100
°C;
V
GS
= 5 V;
Figure 2
I
DM
P
tot
T
stg
T
j
I
DR
I
DRM
peak drain current
total power dissipation
storage temperature
operating junction temperature
reverse drain current (DC)
peak reverse drain current
T
mb
= 25
°C
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs
unclamped inductive load; I
D
= 22 A;
V
DS
≤
55 V; V
GS
= 5 V; R
GS
= 50
Ω;
starting T
j
= 25
°C
T
mb
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
mb
= 25
°C;
Figure 1
[1]
Conditions
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
-
−55
−55
-
-
-
Max
55
55
±10
±15
22
16
90
26
+150
+150
22
90
180
Unit
V
V
V
V
A
A
A
W
°C
°C
A
A
mJ
Source-drain diode
Avalanche ruggedness
E
DS(AL)S
non-repetitive drain-source avalanche
energy
[1]
I
DM
is limited by chip, not package.
9397 750 13326
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 10 June 2004
2 of 12
Philips Semiconductors
BUK9728-55A
N-channel TrenchMOS™ logic level FET
120
Pder
(%)
100
03ne36
120
Ider
(%)
03ne37
100
80
80
60
60
40
40
20
20
0
0
25
50
75
100
125
150 175
Tmb (oC)
0
0
25
50
75
100
125
150 175
o
Tmb ( C)
P
tot
P
der
=
----------------------
×
100%
P
°
tot
(
25 C
)
V
GS
≥
5 V
I
D
I
der
=
------------------
×
100%
-
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
103
ID
(A)
Fig 2. Normalized continuous drain current as a
function of mounting base temperature.
03ne06
102
RDSon = VDS/ ID
tp = 10 us
100 us
10
1 ms
P
δ
=
tp
D.C.
T
10 ms
100 ms
1
tp
t
T
10-1
1
10
VDS (V)
102
T
amb
= 25
°C;
I
DM
is single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 13326
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 10 June 2004
3 of 12
Philips Semiconductors
BUK9728-55A
N-channel TrenchMOS™ logic level FET
7. Thermal characteristics
Table 4:
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Conditions
Figure 4
Min Typ Max Unit
-
-
-
55
4.7
-
K/W
K/W
thermal resistance from junction to
mounting base
Symbol Parameter
thermal resistance from junction to ambient vertical in still air
7.1 Transient thermal impedance
10
Zth(j-mb)
(K/W)
δ
= 0.5
0.2
03ne07
1
0.1
0.05
10-1
0.02
P
δ
=
tp
T
Single Shot
tp
T
t
10-2
10-6
10-5
10-4
10-3
10-2
10-1
1
tp (s)
10
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.
9397 750 13326
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 10 June 2004
4 of 12
Philips Semiconductors
BUK9728-55A
N-channel TrenchMOS™ logic level FET
8. Characteristics
Table 5: Characteristics
T
j
= 25
°
C unless otherwise specified
Symbol
V
(BR)DSS
Parameter
drain-source breakdown
voltage
Conditions
I
D
= 0.25 mA; V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
°C
T
j
= 150
°C
T
j
=
−55 °C
I
DSS
drain-source leakage current
V
DS
= 55 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 150
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state
resistance
V
GS
=
±10
V; V
DS
= 0 V
V
GS
= 5 V; I
D
= 15 A;
Figure 7
and
8
T
j
= 25
°C
T
j
= 150
°C
V
GS
= 4.5 V; I
D
= 15 A
V
GS
= 10 V; I
D
= 15 A
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
L
d
L
s
total gate charge
gate-to-source charge
gate-to-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
internal drain inductance
internal source inductance
from drain lead 6 mm from
package to centre of die
from source lead 6 mm from
package to source bond pad
I
S
= 15 A; V
GS
= 0 V;
Figure 15
I
S
= 20 A; dI
S
/dt =
−100
A/µs
V
GS
=
−10
V; V
DS
= 30 V
V
DD
= 30 V; R
L
= 1.2
Ω;
V
GS
= 5 V; R
G
= 10
Ω
V
GS
= 0 V; V
DS
= 25 V;
f = 1 MHz;
Figure 12
V
GS
= 5 V; V
DD
= 44 V;
I
D
= 15 A;
Figure 14
-
-
-
-
-
-
-
-
-
-
-
-
27
4.2
11.7
1200
210
140
14
125
64
68
4.5
7.5
-
-
-
1725
250
195
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
nH
nH
-
-
-
-
23
-
-
21
28
51
30
25
mΩ
mΩ
mΩ
mΩ
-
-
-
0.05
-
2
10
500
100
µA
µA
nA
1
0.6
-
1.5
-
-
2
-
2.3
V
V
V
55
50
-
-
-
-
V
V
Min
Typ
Max
Unit
Static characteristics
Source-drain diode
V
SD
t
rr
Q
r
9397 750 13326
source-drain (diode forward)
voltage
reverse recovery time
recovered charge
-
-
-
0.85
35
70
1.2
-
-
V
ns
nC
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 02 — 10 June 2004
5 of 12
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