The FTT1010M is a monochrome progressive-scan frame-
transfer image sensor offering 1K x 1K pixels at 30 frames
per second through a single output buffer. The combination
of high speed and a high linear dynamic range (>12 true bits
at room temperature without cooling) makes this device the
perfect solution for high-end real time medical X-ray,
scientific and industrial applications. A second output can
either be used for mirrored images, or can be read out
simultaneously with other output to double the frame rate.
The device structure is shown in figure 1.
Device structure
Z
Optical size:
Chip size:
Pixel size:
Active pixels:
Total no. of pixels:
Optical black pixels:
Timing pixels:
Dummy register pixels:
Optical black lines:
12.288 mm (H) x 12.288 mm (V)
14.572 mm (H) x 26.508 mm (V)
12 µm x 12 µm
1024 (H) x 1024 (V)
1072 (H) x 1030 (V)
Left: 20
Right:20
Left: 4
Right:4
Left: 7
Right: 7
Bottom: 6 Top: 6
6 black lines
Image Section
1024
active
lines
4
20
1024 active pixels
Y
20
4
2060
lines
Storage Section
W
Output
7
amplifier
6 black lines
1072 cells
Output register
X
7
Figure 1 – Device Structure
April 17, 2007
2
DALSA Professional Imaging
Product Specification
1M Frame Transfer CCD Image Sensor
Architecture of the FTT1010M
The FTT1010M consists of a shielded storage section and
an open image section. Both sections are electronically the
same and have the same cell structure with the same
properties. The only difference between two sections is the
optical light shield.
The optical centres of all pixels in the image section form a
square grid. The charge is generated and integrated in this
section. Output registers are located below the storage
section. The output amplifiers Y and Z are not used in Frame
Transfer mode and should be connected as not-used
amplifiers.
After the integration time, the charge collected in the image
section is shifted to the storage section. The charge is read
out line by line through the lower output register.
FTT1010M
The left and the right half of each output register can be
controlled independently. This enables either single or
multiple readout.
During vertical transport, the C3 gates separate the pixels in
the register. The letters W, X, Y, and Z are used to define
the four quadrants of the sensor. The central C3 gates of
both registers are part of the W and Z quadrants of the
sensor.
Both upper and lower registers can be used for vertical
binning. Both registers also have a summing gate at each
end that can be used for horizontal binning. Figure 2 shows
the detailed internal structure.
IMAGE SECTION
Image diagonal (active video only)
Aspect ratio
Active image width x height
Pixel width x height
Fill factor
Image clock pins
Capacity of each clock phase
Number of active lines
Number of black reference lines
Total number of lines
Number of active pixels per line
Number of overscan (timing) pixels per line
Number of black reference pixels per line
Total number of pixels per line
17.38 mm
1:1
12.288 x 12.288 mm
2
12 x 12 µm
2
100%
A1, A2, A3, A4
2.5nF per pin
1024
6
1030
1024
8 (2x4)
40 (2x20)
1072
STORAGE SECTION
Storage width x height
Cell width x height
Storage clock phases
Capacity of each clock phase
Number of cells per line
Number of lines
12.864 x 12.360 mm
2
12 x 12 µm
2
B1, B2, B3, B4
2.5nF per pin
1072
1030
OUTPUT REGISTERS
Output buffers (three-stage source follower)
Number of registers
Number of dummy cells per register
Number of register cells per register
Output register horizontal transport clock pins
Capacity of each C-clock phase
Overlap capacity between neighbouring C-clocks
Output register Summing Gates
Capacity of each SG
Reset Gate clock phases
Capacity of each RG
4 (one on each corner)
2 (one above, one below)
14 (2x7)
1072
C1, C2, C3
60pF per pin
20pF
4 pins (SG)
15pF
4 pins (RG)
15pF
April 17, 2007
3
DALSA Professional Imaging
Product Specification
1M Frame Transfer CCD Image Sensor
FTT1010M
7 dummy pixels
RG
RD
20 black & 4 timing
columns
A1
A2
A3
A4
1K image pixels
20 black & 4 timing
columns
A1
A2
A3
A4
7 dummy pixels
RD
RG
OG SG C2 C1
C3
C2 C1
C3
C2 C1
C3
C2 C1
C3
C2 C1
C3
C2 C1
C3
C3
C1
C3
C2 C1 C1
C3
C2
C2 C1
C3
C2 C1
C3
C2 C1
C3
C2 C1 SG OG
OUT_Z
(not used)
OUT_Y
(not used)
One Pixel
A1
A2
A3
A4
A1
A1
A2
A3
A4
6 black
lines
IMAGE
1K active
images lines
A1
A2
A3
A4
A1
A2
A3
A4
SG: summing gate
OG: output gate
RG: reset gate
RD: reset drain
A1
A2
A3
A4
B1
B2
B3
B4
FT CCD
1K storage
lines
A1
A2
A3
A4
B1
B2
B3
B4
B1
B2
B3
B4
B1
B2
B3
B4
B1
B2
B3
B4
B1
B2
B3
B4
STORAGE
6 black
lines
OUT_W
OG SG C2 C1
C3
RG
RD
B1
B2
B3
B4
B1
B1
B2
B3
B4
B1
C3
C2 C1
C3
C2 C1
C3
C2 C1
C3
C2 C1
C3
C2 C1
C3
OUT_X
C2 C1 SG OG
RG
RD
C2 C1
C3
C2 C1
C3
C2 C1
C3
C2 C1
C3
C2 C1
C3
column
1
A1, A2, A3, A4: clocks of image section
column
24 + 1
column
24 + 1K
column
24 +1K +24
C1, C2, C3: clocks of horizontal registers
B1, B2, B3, B4: clocks of storage section
Figure 2 - Detailed internal structure
April 17, 2007
4
DALSA Professional Imaging
Product Specification
1M Frame Transfer CCD Image Sensor
Specifications
ABSOLUTE MAXIMUM RATINGS
1
GENERAL:
storage temperature
ambient temperature during operation
voltage between any two gates
DC current through any clock (absolute value)
OUT current (no short circuit protection)
VOLTAGES IN RELATION TO VPS:
VPS, SFD, RD
VCS, SFS
All other pins
VOLTAGES IN RELATION TO VNS:
SFD, RD
VCS, SFS, VPS
All other pins
DC CONDITIONS
VNS
4
VPS
SFD
SFS
VCS
OG
RD
2,3
FTT1010M
MAX
UNIT
MIN
-55
-40
-20
-0.2
0
-0.5
-8
-5
-15
-30
-30
MIN [V]
20
1
16
-
-5
4
13
2
+80
+60
+20
+0.2
10
+30
+5
+25
+0.5
+0.5
+0.5
TYPICAL [V]
24
3
20
0
0
6
15.5
TYPICAL
MAX [V]
28
7
24
-
3
8
18
MAX
ºC
ºC
V
µA
mA
V
V
V
V
V
V
MAX [mA]
15
15
4.5
1
−
−
−
UNIT
N substrate
P substrate
Source Follower Drain
Source Follower Source
Current Source
Output Gate
Reset Drain
AC CLOCK LEVEL CONDITIONS
MIN
IMAGE CLOCKS:
A-clock amplitude during integration and hold
A-clock amplitude during vertical transport (duty cycle=5/8)
A-clock low level
Charge Reset (CR) level on A-clock
STORAGE CLOCKS:
B-clock amplitude during hold
B-clock amplitude during vertical transport (duty cycle=5/8)
OUTPUT REGISTER CLOCKS:
C-clock amplitude (duty cycle during hor. transport=3/6)
C-clock low level
Summing Gate (SG) amplitude
Summing Gate (SG) low level
OTHER CLOCKS:
Reset Gate (RG) amplitude
Reset Gate (RG) low level
Charge Reset (CR) pulse on Nsub
1
2
8
5
10
14
0
-5
10
14
5
3.5
10
3.5
10
5.25
V
V
V
V
V
V
V
V
V
V
10
10
V
V
V
10
-5
8
10
4.75
2
6
5
6
10
3
10
0
During Charge Reset it is allowed to exceed maximum rating levels (see note 5)
All voltages in relation to SFS
3
Power-up sequence: VNS, SFD, RD, VPS, others
4
To set the VNS voltage for optimal Vertical Antiblooming (VAB), it should be adjustable between minimum and maximum values
5
Three-level clock is preferred for maximum charge; the swing during vertical transport should be 4V higher than the voltage during integration
A two level clock (typically 10V) can be used if a lower maximum charge handling capacity is allowed
6
Charge Reset can be achieved in two ways:
•
The typical CR level is applied to all image clocks simultaneously (preferred).
•
The typical A-clock low level is applied to all image clocks; for proper CR, an additional Charge Reset pulse on VNS is required. This will also affect
the charge handling capacity in the storage areas.
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