PDSP16510A
PDSP16510A
Stand Alone FFT Processor
DS3475
ISSUE 4.4
May 1996
The PDSP16510 performs Forward or Inverse Fast
Fourier Transforms on complex or real data sets containing up
to 1024 points. Data and coefficients are each represented by
16 bits, with block floating point arithmetic for increased
dynamic range.
An internal RAM is provided which can hold up to 1024
complex data points. This removes the memory transfer
bottleneck, inherent in building block solutions. Its organisa-
tion allows the PDSP16510 to simultaneously input new data,
transform data stored in the RAM, and to output previous
results. No external buffering is needed for transforms con-
taining up to 256 points, and the PDSP16510 can be directly
connected to an A/D converter to perform continuous trans-
forms. The user can choose to overlap data blocks by either
0%, 50%, or 75%. Inputs and outputs are synchronous to the
40MHz system clock used for internal operations.
A 1024 point complex transform can be completed in
some 98µs, which is equivalent to throughput rates of 450
million operations per second. Multiple devices can be con-
nected in parallel in order to increase the sampling rate up to
the 40MHz system clock. Six devices are needed to give the
maximum performance with 1024 point transforms.
Either a Hamming or a Blackman-Harris window operator
can be internally applied to the incoming real or complex data.
The latter gives 67dB side lobe attenuation. The operator
values are calculated internally and do not require an external
ROM nor do they incur any time penalty.
The device outputs the real and imaginary components of
the frequency bins. These can be directly connected to the
PDSP16330 in order to produce magnitude and phase values
from the complex data.
DATA INPUT
3 TERM
WINDOW
OPERATOR
COEFFICIENT
ROM
WORKSPACE
RAM
WORKSPACE
RAM
FOUR
DATA PATHS
OUTPUT
BUFFER
RESULT OUPUT
Fig. 1. Block Diagram
FEATURES
Completely self contained FFT Processor
Internal RAM supports up to1024 complex points
16 bit data and coefficients plus block floating point for
increased dynamic range
450 MIP operation gives 98 microsecond transforma-
tion times for 1024 points
ASSOCIATED PRODUCTS
PDSP16540
Bucket Buffer
PDSP16330
Pythagoras Processor.
PDSP16256
Programmable FIR Filter.
PDSP16350
I/Q Splitter / NCO
Up to 40MHz sampling rates with multiple devices.
Internal window operator gives 67dB side lobe
attenuation and needs no external ROM.
84 pin PGA or 132 surface mount package
SAMPLE
CLOCK
CONFIGURATION
WORD
DIS
AUX15:0
GND
INEN
DOS
R15:0
X
CLK
PHASE
ANALOG
INPUT
PDSP16510
A/D
D15:0
I15:0
Y
DEF DEN DAV S3:0
GND
RESET
PDSP16330
MAGNITUDE
SCALE VALUE
AVAILABLE
1
Fig. 2. Typical 256 Point Real Only System Performing Continuous Transforms
PDSP16510A
N
D9
D10
D12
D14
DIS
VDD
DAV
GND
AUX0
AUX2
AUX4
AUX6
AUX7
M
D8
D11
D13
D15
DEF
INEN
SCLK
AUX1
AUX3
AUX5
AUX8
L
D6
D7
AUX9
AUX10
K
D4
D5
AUX11
AUX12
J
D2
D3
AUX13
AUX14
H
GND
D1
AUX15
GND
G
D0
LFLG
DEN
I15
F
VDD
R0
I14
VDD
E
R1
R2
I12
I13
D
R3
R4
I10
I11
C
R5
R6
I8
I9
B
R7
R10
R12
R14
S0
DOS
S2
I0
I2
I4
I7
A
R8
R9
R11
R13
R15
VDD
S1
GND
S3
I1
I3
I5
I6
Pin Out for 84 PGA Package (AC84) - bottom view
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
FUNC
VDD
GND
I7
I8
I9
I10
VDD
I11
GND
I12
VDD
I13
GND
I14
VDD
I15
GND
DEN
AUX15
GND
AUX14
GND
PIN
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
FUNC
AUX13
VDD
AUX12
GND
AUX11
VDD
GND
AUX10
AUX9
AUX8
AUX7
VDD
AUX6
VDD
AUX5
GND
AUX4
AUX3
AUX2
VDD
AUX1
AUX0
PIN
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
FUNC
GND
VDD
SCLK
GND
GND
DAV
GND
INEN
VDD
DEF
GND
DIS
VDD
D15
D14
GND
D13
D12
D11
D10
VDD
D9
PIN
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
FUNC
D8
D7
D6
D5
GND
VDD
D4
GND
D3
VDD
D2
GND
D1
VDD
D0
LFLG
GND
R0
GND
R1
VDD
R2
PIN
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
FUNC
GND
R3
VDD
R4
GND
R5
R6
R7
R8
GND
VDD
R9
VDD
R10
R11
R12
R13
GND
R14
R15
DISAB
S0
PIN
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
FUNC
GND
S1
GND
DOS
DOS
VDD
S2
GND
S3
GND
VDD
I0
I1
GND
I2
I3
I4
GND
VDD
I5
I6
VDD
2
Pin Out for 132 Leaded Chip Carrier (GC132)
PDSP16510A
SIGNAL
D15:0
AUX15:0
TYPE
I
I
DESCRIPTION
Data input during real only mode. The real component in complex data mode.
When DEF is active AUX15:0 are used to define the operating mode as defined in Table 3.
When DEF is in-active AUX15:0 either provide the 16 bit imaginary component of complex
input data, or a second set of real only inputs.
These pins output the real component of the transformed data when DAV and DEN are active.
Otherwise they are high impedance.
These pins output the imaginary component of the transformed data when DAV and DEN are
active. Otherwise they are high impedance.
The high going edge of DEF is used to internally latch the contents of AUX15:0, which then
define the operating mode. In the simplest system DEF is a power on reset. When DEF is low
the internal control logic is reset.
System clock used for internal computations.
These pins indicate the number of shifts towards the binary point which have occurred as the
result of the conditional scaling logic. When the data path right shift is restricted to 2 places
per pass, state 15 is used to indicate an overflow and only a total of 14 shifts is possible.
This flag indicates that data is being loaded into the device. It goes active in response to an
INEN input, and may be programmed to go in-active after the complete, one quarter, or one
half a data block has been loaded.
The use of this input is mode dependent. It is either used as an active low, load enabling,
signal for the DIS strobe, or it is used to initiate a new block load operation.
The rising edge of this input is used to load data into the device.
The rising edge of this input is used to dump data from the device. In most applications it may
be tied to the DIS input, even if the output rate must be higher than the input rate because of
overlapped data blocks. The DIS input is then internally divided down.
An active low signal that indicates that a transform is complete. Transformed data will then
be output in normal sequential order using DOS. It may be optionally programmed to be
delayed by 24 DOS strobes to match the delay through a PDSP16330.
This input is used to enable the data dump operation when DAV has gone active. If it is tied
low the device will automatically dump data when DAV goes active. Otherwise the device will
wait for the enabling signal to go low before the dump operation commences.
Only available in the 132 pin GC package. When high the block floating logic is disabled.
+5V pins
Ground pins
R15:0
O
I15:0
O
DEF
I
SCLK
S3:0
I
O
LFLG
O
INEN
I
DIS
DOS
I
I
DAV
O
DEN
I
DISAB
VDD
GND
I
P
P
NOTE.
All references to DEF, INEN, DAV, and DEN within the text do not contain the bar designator, signifying an active low
signal. This is considered to be implied by the signal name and is not meant to imply a change in the signal function.
FUNCTIONAL OPERATION
The PDSP16510 performs decimation in time, radix 4,
forward or inverse Fast Fourier Transforms. Data is loaded
into an internal workspace RAM in normal sequential order,
processed, and then dumped in the correct order. With real
only input data the processing time can approximately be
halved for a given transform size. Two real inputs then replace a
single complex input, and are processed in parallel.
Either a Blackman-Harris or a Hamming window can be
generated internally, and applied to the incoming real or complex
data with no time penalty. No external ROM is needed to support
these windows. The Blackman-Harris window gives improved
dynamic range over the Hamming window when two closely
3
PDSP16510A
spaced frequencies are to be detected, and one is of smaller
magnitude than the other. It does, however, reduce the actual
frequency resolution, and the Hamming window may then be
preferable.
Data in and out of the device is represented by 16 bit real
and imaginary components, with 16 bit sine and cosine values
contained in an internal ROM. Conditional scaling, coupled
with word growth through the butterfly data path, gives in-
creased dynamic range. Transforms can be computed with
sample sizes of either 256 or 1024 data points. The 256 point
option can alternatively be used to simultaneously execute
either four 64 point transforms, or sixteen 16 point transforms.
The 16 point mode can only be used with a rectangular
window, and no overlapping of data blocks is possible.
The device can be configured, either, to perform continu-
ous transforms in a real time application, or as slave processor
to a more general purpose signal processing system. In the
continuous mode, with transform sizes of 256 points or less,
it contains three internal control units which simultaneously
allow new data to be loaded, present data to be transformed,
and previous results to be dumped. Additional, external, input/
output buffering is not needed. The internal input buffer also
allows data blocks to be overlapped by either 50% or 75%,
apart from the mode with no overlaps.
When 1024 point transforms are to be calculated, without
loss of incoming data during the transform time, it is necessary
to use an input buffer. This requirement is satisfied by a single
PDSP16540 support device.
In any of the real or complex modes it is possible to obtain
higher performance by connecting devices in parallel. It is then
possible to increase the sampling rate to that of the system
clock used for internal operations.
The mode of operation of the device is controlled by 16
bits in a control register. These are loaded through the
AUX15:0 port when a control signal DEF is active low. This
port is also used to provide the imaginary component of
complex input data, and, if complex transforms are to be
performed, an external tristate buffer will be needed to isolate
the control information. This should only be enabled when
DEF is active. DEF is also used to initialise the internal
circuitry, and can be a simple power on reset if control
parameters need not be subsequently changed.
INPUT
SELECT
RAM
SIN / COS
ROM
Shift left until largest point
has one sign bit.
16
16
MULTIPLIER
S
S
29 - 14 13 - 0
"1"
18
16
FIRST ADDER
19Bit Result
18 - 1
0
REGISTER FILE
SECOND ADDER
19Bit Result
18 - 1
0
REGISTER FILE
THIRD ADDER
19Bit Result
18 - 3
17 - 2
DATA PRECISION
During each pass of a radix-4 fast Fourier transform it is
possible for either component of a particular result to grow by
a factor of up to four in the first pass, and 5.242 in subsequent
passes. This is between two and three bits in each pass and
the data path must allow for this word growth to avoid any
possibility of overflow. At the end of the data path the word is
again reduced to 16 bits by discarding least significant bits.
Any un-necessary word growth to prevent overflow thus
results in loss of arithmetic precision, and has a detrimental
effect on the dynamic range achievable.
In practice these large word growths only occur when
bipolar complex square waves are transformed, and even
then will not occur on every pass. The PDSP16510 compro-
mises by allowing a 2 bit word growth during the butterfly
calculation in the first pass. This is equivalent to ignoring the
most significant bit of the 19 bit final result, which is assumed
to be an extra sign bit, and then selecting the next 16 bits for
CR
BIT3
SELECT
Fig. 3 One of Four Data Paths
storage. In subsequent passes a Control Register Bit allows
the user to continue to select these 16 bits, or instead to use
the 16 most significant bits. The latter option is equivalent to
a 3 bit word growth. The 2 or 3 bit word growth option applies
to ALL subsequent passes and is not a per pass option.
If the 2 bit option is selected there is a possibility of
overflow occurring in one of the passes. The prediction of
overflow is mathematically difficult, and only occurs with
specific complex square waves. Scaling down the inputs
cannot be guaranteed to prevent overflow because of the
4
PDSP16510A
block floating point shifting scheme, which is discussed later.
Overflow can NEVER occur if the 3 bit option is chosen, but at
the expense of worse dynamic range.
When overflow does occur a flag is raised which can be
read by the user ( see later discussion on scale tag bits ), and
the results ignored. In addition all frequency bins are forced
to zero to prevent any erroneous system response.
Even with only 2 bit word growth poor dynamic range will
be obtained if the data is simply reduced to 16 bits, and
becomes worse when the incoming data does not fully occupy
all the bits in the word. These problems are overcome in the
PDSP16510, however, by a block floating point scheme which
compensates for any unnecessary word growth.
During each pass the number of sign bits in the largest
result is recorded. Before the next pass, data is shifted left
[multiplied by 2], once for every extra sign bit in this recorded
sample. At least one component in the block then fully occu-
pies the 16 bit word, and maximum data accuracy is preserved
Up to four shifts are possible before every pass after the
first, with a total of fifteen for the complete transform. At the end
of the transform the number of left shifts that have occurred is
indicated on S3:0. Lack of pins prevents a separate output
being available to indicate that overflow has occurred in the 2
bit word growth option. For this reason the maximum number
of compensating left shifts in this mode is restricted to 14.
State 15 is then used to indicate that overflow has occurred.
The first step in the butterfly calculation multiplies 16 bit
data values with 16 bit sine/cosine values, to give 18 bit
results. This increased word length preserves accuracy
through the following adder network, and has been shown
through simulations to be an optimum size for transform sizes
up to 1024 points. This is particularly true when the input data
is restricted to below 16 bits, as is necessary with practical A/
D converters with very high sampling rates. The bottom bit of
this 18 bit word is forced to logical one and as such is a
compromise between truncation and true rounding. It gives a
lower noise floor in the outputs compared to simple truncation.
To prevent any possibility of overflow during the butterfly
calculation the word length is allowed to grow by one bit
through each of the three adders. The least significant bit is
always discarded in the first two adders . Sixteen bits are then
chosen from the final adder in the manner discussed earlier,
and the number of sign bits in the largest result is recorded for
use in the following pass.
Fig. 3 shows one of the four internal data paths which can
compute a radix-4 butterfly in twelve system clock cycles. This
equates to completing the butterfly in 3 cycles for the complete
device.
TRANS-
FORM
WORKSPACE
INPUT
DATA
FFT
DATA PATH
OUTPUT
LOAD
Fig. 5. RAM Organization with 1024 Point Transforms
RAM has been designed for use in a wide variety of applica-
tions. The provision of an independent input strobe (DIS),
allows data to be loaded without the need for additional
external buffering. An independent output strobe (DOS) is
also provided. DIS and DOS can thus be tied together, this
being particularly useful when the device is performing the
inverse transform back to the time domain. Transfer of data
occurs internally from DIS to SCLK, so although thay can be
of different frequencies, they must be synchronous to each
other. In the same way transfer of data also occurs from SCLK
to DOS, so while DOS can also be independent of SCLK it
must also be synchronous to it. Inputs and outputs are both
supported by flag and enabling signals which allow transfers
to be properly co-ordinated with the internal transform opera-
tion.
In many applications the DIS and DOS inputs can be tied
together and fed by the sampling clock. If the output rate must
be higher than the input rate, as with multiple devices support-
ing overlapped data samples, both strobes can still be con-
nected together. The clock supplied should then be twice or
four times the sampling clock, and an internal divider can be
used to provide the correctly reduced input rate. The provision
of a separate DOS pin does, however, allow the output rate to
be different to the input rate, and therefore faster than strictly
needed. Further output processing at higher rates is then
possible if this is advantageous to system requirements.
The internal workspace is double buffered when 256
point transforms are to be performed. A separate output buffer
is also provided. These resources, together with separate
input and output buses, allow new data to be loaded and old
results to be dumped, whilst the present transform is being
computed. Additional, external, input buffering is not needed
to prevent loss of incoming data whilst a transform is being
performed.
When block overlapping is required, internally stored
data will be re-used, and a proportionally smaller number of
new samples need be loaded. Note that the internal window
operator still functions correctly since it is actually applied
during the first pass, and not whilst data is being loaded. The
internal RAM organisation is
RESET
SAMPLE CLOCK
POWER ON
shown in Fig. 4. It should be
510 PARAMETERS
DATA TRANSFERS
GND
GND
DAV
DEF
WEN
WS
RES
AUX
DEN
I
The data transfer mechanism to and from the internal
IMAG'
PDSP16540
BUCKET
BUFFER
PDSP16510
INEN
SCLK
DOS
D
R
RS MD5:0 DAV
FFT
DATA PATH
O/P
BUFFER
INPUT
DATA
LOAD
WORKSPACE
B
SYSTEM
CLOCK
GND
LOAD IN
LAST PASS
TRANS-
FORM
Fig. 4. RAM Organization with 256 Data Points
Fig. 6. 1024 Point Transforms with I/P Buffer
DIS
WORKSPACE
A
REAL
5
Sensor
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