improve power conversion efficiency across the entire load
range. Zilker Labs Digital-DC™ technology enables a blend of
power conversion performance and power management
features.
The ZL8101 is designed to be a flexible building block for DC
power and can be easily adapted to designs ranging from a
single-phase power supply operating from a 4.5V input to a
multi-phase supply operating from a 12V input. The ZL8101
eliminates the need for complicated power supply managers
as well as numerous external discrete components.
Most operating features can be configured by simple
pin-strap/resistor selection or through the SMBus™ serial
interface. The ZL8101 uses the PMBus™ protocol for
communication with a host controller and the Digital-DC bus
for communication between other Zilker Labs devices.
FN7832
Rev 1.00
July 13, 2012
Features
• Efficient Synchronous Buck Controller
• Adaptive Performance Optimization Algorithms
• ±1% Output Voltage Accuracy
• Auto Compensation
•
Snapshot™
Parametric Capture
• I
2
C/SMBus Interface, PMBus Compatible
• Internal Non-Volatile Memory (NVM)
• Tri-State PWM Gate Outputs
• Compatible with Industry Standard DrMOS Devices
• Compatible with Intersil ISL6611 Phase Doubler
• Synchronized External Driver Control
Applications
• Servers/Storage Equipment
• Telecom/Datacom Equipment
• Power Supplies (Memory, DSP, ASIC, FPGA)
Related Literature
•
AN2033
“Zilker Labs PMBus Command Set - DDC Products”
•
AN2034
“Configuring Current Sharing on the ZL2004 and
ZL2006”
•
AN2010
“Thermal and Layout Guidelines for Digital-DC™
Products”
96
V
OUT
= 3.3V
91
EFFICIENCY (%)
V
OUT
= 1.5V
86
V
OUT
= 1.0V
V
OUT
= 1.2V
V
IN
= 12V
f
SW
= 400kHz
L = 0.45µH
G
H
= 1 x BSC050NE2Ls
G
L
= 2 x BSC010NE2LS
2
4
6
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
OUTPUT CURRENT (A)
V
OUT
= 1.8V
V
OUT
= 2.5V
81
76
FIGURE 1. EFFICIENCY vs LOAD CURRENT
FN7832 Rev 1.00
July 13, 2012
Page 1 of 36
ZL8101
Block Diagram
EN PG SS
FC
V25 VR VDD
V (0, 1)
VMON
MGN
SYNC
DDC
DRVCTL
POWER
MANAGEMENT
LDO
LEVEL
SHIFTER
NON-
VOLATILE
MEMORY
PWM
CONTROLLER
PWMH
PWML
ISENA
ISENB
CURRENT
SENSE
TEMP
SENSOR
SCL
SDA
SALRT
I
2
C
MONITOR
ADC
SA (0,1)
VTRK
VSEN
XTEMP SGND DGND
Ordering Information
PART NUMBER
(Notes 1, 2)
ZL8101ALAFT
ZL8101ALAFTK
ZL8101ALAF
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For Moisture Sensitivity Level (MSL), please see device information page for
ZL8101.
For more information on MSL please see techbrief
TB363.
PART
MARKING
8101
8101
8101
TEMP. RANGE
(°C)
-40 to +85
-40 to +85
-40 to +85
PACK
METHOD
Tape and Reel 6k
Tape and Reel 1k
Bulk
PACKAGE
32 Ld QFN
32 Ld QFN
32 Ld QFN
PKG.
DWG. #
L32.5x5G
L32.5x5G
L32.5x5G
ZL Types
ZL BBBBB
ZL = ZILKER LABS DESIGNATOR
BASE PART NUMBER
5 Character Max.
PACKAGE DESIGNATOR
A: (QFN)
OPERATING TEMPERATURE RANGE
J: (0°C to +85°C)
K: (0 to +70°C)
L: (-40°C to +85°C)
Z: (-55°C to +125°C)
P
T
S
L
F
-CC
CUSTOM CODE
Any alphanumeric character
SHIPPING OPTION
J: (Trays)
T1 or TK: (Tape and Reel - 1000 piece)
T3: (Tape and Reel - 3000 piece)
T4: (Tape and Reel - 4000 piece)
T5: (Tape and Reel - 5000 piece)
T6: (Tape and Reel - 6000 piece)
T: (Tape and Reel - 100 piece for
Zilker legacy products)
T: (Tape and Reel - Full reel Qty.
for Intersil Zilker products)
W: (Waffle pack)
LEAD FINISH
F (Lead-free Matte Tin)
N (Lead-free NiPdAu)
FIRMWARE REVISION
Any alphanumeric character
FN7832 Rev 1.00
July 13, 2012
Page 2 of 36
ZL8101
Pin Configuration
ZL8101
(32 LD QFN)
TOP VIEW
XTEMP
26
MGN
DDC
V25
25
24 VDD
23 VR
22 PWMH
21 SGND
EXPOSED PADDLE*
5
6
7
8
9
FC
10
V0
11
V1
12
VMON
13
DRVCTL
14
VTRK
15
VSEN+
16
VSEN-
20 PWML
19 ISENA
18 ISENB
17 NC
NC
29
PG
EN
30
SS
31
32
DGND
SYNC
SA0
SA1
NC
SCL
SDA
SALRT
1
2
3
4
28
27
*CONNECT TO SGND
Pin Descriptions
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
LABEL
DGND
SYNC
SA0
SA1
NC
SCL
SDA
SALRT
FC
V0
V1
VMON
DRVCTL
VTRK
VSEN+
VSEN-
NC
ISENB
ISENA
I
I
I/O
I/O
O
I
I, M
I, M
O
I
I
I
TYPE
(Note 3)
PWR
I/O, M
(Note 4)
I, M
DESCRIPTION
Digital ground. Connect to low impedance contiguous ground plane.
Clock synchronization input. Used to set the frequency of the internal switch clock, to sync to an external
clock or to output internal clock.
Serial address select pins. Used to assign a unique address for each individual device or to enable certain
management features.
No Connect. Leave pin open.
Serial clock. Connect to external host and/or to other ZL devices.
Serial data. Connect to external host and/or to other ZL devices.
Serial alert. Connect to external host if desired.
Auto compensation configuration pin. Used to set up auto compensation.
Output voltage selection pins. Used to set V
OUT
set-point and V
OUT
max.
External voltage monitoring (can be used for external driver bias monitoring for Power-Good).
External driver enable control output.
Tracking sense input. Used to track an external voltage source.
Differential Output voltage sense feedback. Connect to positive output regulation point.
Differential Output voltage sense feedback. Connect to negative output regulation point.
No Connect. Leave pin open.
Differential voltage input for current sensing.
Differential voltage input for current sensing. High voltage (DCR).
FN7832 Rev 1.00
July 13, 2012
Page 3 of 36
ZL8101
Pin Descriptions
PIN
20
21
22
23
24
25
26
27
28
29
30
31
32
PD
NOTES:
LABEL
PWML
SGND
PWMH
VR
VDD
(Note 5)
V25
XTEMP
DDC
MGN
NC
EN
SS
PG
SGND
I
I, M
O
PWR
O
PWR
O
PWR
PWR
PWR
I
I
I
(Continued)
DESCRIPTION
PWM Gate low signal.
Connect to low impedance ground plane. Internal connection to SGND.
PWM Gate High signal.
Internal 5V Reference.
Supply voltage.
Internal 2.5V reference used to power internal circuitry.
External temperature sensor input. Connect to external 2N3904 (Base Emitter junction).
Single wire DDC bus (Current sharing, inter device communication).
V
OUT
margin control.
No Connect. Leave pin open.
Enable. Active signal enables PWM switching.
Soft-start delay and ramp select. Sets the delay from when EN is asserted until the output voltage starts to
ramp and the ramp time.
Power-Good output.
Exposed thermal pad. Connect to low impedance ground plane. Internal connection to SGND.
TYPE
(Note 3)
3. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins (refer to “Multi-mode Pins” on page 12).
4. The SYNC pin can be used as a logic pin, a clock input or a clock output.
5. The V
DD
pin voltage is used to measure V
IN
as part of the Pre-Bias calculation and Loop Gain calculation used for current sharing ramps.