®
49%
FPO
PCM1702P
PCM1702U
BiCMOS Advanced Sign Magnitude 20-Bit
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q
ULTRA LOW –96dB max THD+N
(No External Adjustment Required)
q
q
q
q
q
NEAR-IDEAL LOW LEVEL OPERATION
GLITCH-FREE OUTPUT
120dB SNR TYP (A-Weight Method)
INDUSTRY STD SERIAL INPUT FORMAT
FAST (200ns) CURRENT OUTPUT
(
±
1.2mA)
DESCRIPTION
The PCM1702 is a precision 20-bit digital-to-analog
converter with ultra-low distortion (–96dB typ with a
full scale output). Incorporated into the PCM1702 is
an advanced sign magnitude architecture that elimi-
nates unwanted glitches and other nonlinearities around
bipolar zero. The PCM1702 also features a very low
noise (120dB typ SNR: A-weighted method) and fast
settling current output (200ns typ, 1.2mA step) which
is capable of 16X oversampling rates.
Applications include very low distortion frequency
synthesis and high-end consumer and professional
digital audio applications.
q
CAPABLE OF 16X OVERSAMPLING
q
COMPLETE WITH REFERENCE
q
LOW POWER (150mW typ)
Clock
Data
LE
DCOM
ACOM
+V
CC
–V
CC
Input Shift Register
and Control Logic
Balanced Current
Segment DAC A
Balanced Current
Segment DAC B
Reference
and
Servo
Bipolar Offset
I
OUT
RF DC
SERV DC
BPO DC
International Airport Industrial Park • Mailing Address: PO Box 11400
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP •
© 1993 Burr-Brown Corporation
• Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
PDS-1175B
Printed in U.S.A. June, 1995
®
1
PCM1702
SBAS026
SPECIFICATIONS
All specifications at 25°C,
±V
CC
and +V
DD
=
±5V
unless otherwise noted.
PCM1702P/U, -J, -K
PARAMETER
RESOLUTION
DYNAMIC RANGE, THD + N at –60dB Referred to Full Scale, with A-weight
DIGITAL INPUT
Logic Family
Logic Level: V
IH
V
IL
I
IH
I
IL
Data Format
Input Clock Frequency
TOTAL HARMONIC DISTORTION + N
(2)
P/U
V
O
= 0dB
V
O
= –20dB
V
O
= –60dB
P/U, -J
V
O
= 0dB
V
O
= –20dB
V
O
= –60dB
P/U, -K
V
O
= 0dB
V
O
= –20dB
V
O
= –60dB
ACCURACY
Level Linearity
Gain Error
Bipolar Zero Error
(5)
Gain Drift
Bipolar Zero Drift
Warm-up Time
IDLE CHANNEL SNR
(6)
ANALOG OUTPUT
Output Range
Output Impedance
Settling Time
Glitch Energy
POWER SUPPLY REQUIREMENTS
Supply Voltage Range: +V
CC
= +V
DD
–V
CC
= –V
DD
Combined Supply Current: +I
CC
Combined Supply Current: –I
CC
Power Dissipation
TEMPERATURE RANGE
Operating
Storage
CONDITIONS
MIN
20
110
TTL/CMOS Compatible
+2.4
0
V
IH
= +V
DD
V
IL
= 0V
+V
DD
0.8
±10
±10
Serial, MSB First, BTC
(1)
12.5
20.0
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
f
S
= 352.8kHz
(3)
, f = 1002Hz
(4)
At –90dB Signal Level
–92
–82
–46
–96
–83
–48
–100
–84
–50
±0.5
±0.5
±0.25
±25
±5
1
110
120
±1.2
1.0
200
No Glitch Around Zero
+4.75
–4.75
+V
CC
= +V
DD
= +5V
–V
CC
= –V
DD
= –5V
±V
CC
=
±V
DD
=
±5V
–25
–55
+5.00
–5.00
+5.00
–25.00
150
+5.25
–5.25
+9.0
–41.0
250
+85
+125
–88
–74
–40
–92
–76
–42
–96
–80
–44
V
V
µA
µA
MHz
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
%
%
ppm of FSR/°C
ppm of FSR/°C
minute
dB
mA
kΩ
ns
TYP
MAX
UNITS
Bits
dB
±3
0°C to 70°C
0°C to 70°C
Bipolar Zero, A-weighted Filter
(±0.003% of FSR, 1.2mA Step)
V
V
mA
mA
mW
°C
°C
NOTES: (1) Binary Two’s Complement coding. (2) Ratio of (Distortion
RMS
+ Noise
RMS
) / Signal
RMS
. (3) D/A converter sample frequency (8 x 44.1kHz; 8x oversampling).
(4) D/A converter output frequency (signal level). (5) Offset error at bipolar zero. (6) Measured using an OPA627 and 5kΩ feedback and an A-weighted filter.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
PCM1702
2
ABSOLUTE MAXIMUM RATINGS (DIP Package)
Power Supply Voltage ..................................................................
±6.5VDC
Input Logic Voltage ........................................... DGND—0.3V~+V
DD
+0.3V
Operating Temperature ..................................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Power Dissipation .......................................................................... 500mW
Lead Temperature (soldering, 10s) .................................................. 260°C
ABSOLUTE MAXIMUM RATINGS (SOP Package)
Power Supply Voltage ..................................................................
±6.5VDC
Input Logic Voltage ........................................... DGND—0.3V~+V
DD
+0.3V
Operating Temperature ..................................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Power Dissipation .......................................................................... 300mW
Lead Temperature (soldering, 5s) .................................................... 260°C
PIN ASSIGNMENTS (DIP Package)
PIN
1
2
3
4
5
6
7
8
MNEMONIC
DATA
CLOCK
+V
DD
DCOM
–V
DD
LE
NC
NC
PIN
9
10
11
12
13
14
15
16
MNEMONIC
+V
CC
BPO DC
I
OUT
ACOM
ACOM
SERV DC
REF DC
–V
CC
PIN ASSIGNMENTS (SOP Package)
PIN
1
2
3
4
5
6
7
8
9
10
MNEMONIC
DATA
CLOCK
NC
+V
DD
DCOM
–V
DD
LE
NC
NC
NC
PIN
11
12
13
14
15
16
17
18
19
20
MNEMONIC
+V
CC
BPO DC
NC
I
OUT
ACOM
ACOM
SERV DC
NC
RFE DC
–V
CC
PACKAGE INFORMATION
(1)
MODEL
PCM1702P
PCM1702U
PACKAGE
16-Pin Plastic DIP
20-Pin Plastic SOP
PACKAGE DRAWING
NUMBER
180
248
GRADE MARKING (SOP Package)
MODEL
PCM1702U
PCM1702U-J
PCM1702U-K
PACKAGE
Marked PCM1702.
Marked with white dot by pin 10.
Marked with red dot by pin 10.
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
CONNECTION DIAGRAM
47µF
+
CLOCK
DATA
LE
+5V V
DD
47µF
47µF
–5V V
DD
+
+
2
1
7
4
5
6
2
1
6
3
4
5
16 20
15 19
14 17
11 14
10 12
9
11
+
+5V V
CC
47µF
47µF
+
+
22µF
100µF
+
–5V V
CC
R
NF
V
OUT
13 16
12 15
= SOP
= DIP
®
3
PCM1702
THEORY OF OPERATION
ADVANCED SIGN MAGNITUDE
Digital audio systems have traditionally used laser-trimmed,
current-source DACs in order to achieve sufficient accuracy.
However, even the best of these suffer from potential low-
level nonlinearity due to errors at the major carry bipolar
zero transition. More recently, DACs employing a different
architecture which utilizes noise shaping techniques and
very high over-sampling frequencies, have been introduced
(“Bitstream”, “MASH”, or 1-bit DAC). These DACs over-
come the low level linearity problem, but only at the expense
of signal-to-noise performance, and often to the detriment of
channel separation and intermodulation distortion if the
succeeding circuitry is not carefully designed.
The PCM1702 is a new solution to the problem. It combines
all the advantages of a conventional DAC (excellent full
scale performance, high signal-to-noise ratio and ease of
use) with superior low-level performance. Two DACs are
combined in a complementary arrangement to produce an
extremely linear output. The two DACs share a common
reference, and a common R-2R ladder for bit current sources
by dual balanced current segments to ensure perfect tracking
under all conditions. By interleaving the individual bits of
each DAC and employing precise laser trimming of resis-
tors, the highly accurate match required between DACs is
achieved.
This new, complementary linear or advanced sign magni-
tude approach, which steps away from zero with small steps
in both directions, avoids any glitching or “large” linearity
errors and provides an absolute current output. The low level
performance of the PCM1702 is such that real 20-bit reso-
lution can be realized, especially around the critical bipolar
zero point.
Table 1 shows the conversion made by the internal logic of
the PCM1702 from binary two’s complement (BTC). Also,
the resulting internal codes to the upper and lower DACs
(see front page block diagram) are listed. Notice that only
the LSB portions of either internal DAC are changing
around bipolar zero. This accounts for the superlative per-
formance of the PCM1702 in this area of operation.
DISCUSSION OF
SPECIFICATIONS
DYNAMIC SPECIFICATIONS
Total Harmonic Distortion + Noise
The key specifications for the PCM1702 is total harmonic
distortion plus noise (THD+N).
Digital data words are read into the PCM1702 at eight times
the standard compact disk audio sampling frequency of
44.1kHz (352.8kHz) so that a sine wave output of 1002Hz
is realized.
For production testing, the output of the DAC goes to an
I to V converter, then through a 40kHz low pass filter, and
then to a programmable gain amplifier to provide gain at
lower signal output test levels before being fed into an
analog-type distortion analyzer. Figure 1 shows a block
diagram of the production THD+N test setup.
For the audio bandwidth, THD+N of the PCM1702 is
essentially flat for all frequencies. The typical performance
curve, “THD+N vs Frequency”, shows four different output
signal levels: 0dB, –20dB, –40dB, and –60dB. The test
signals are derived from a special compact test disk (the
CBS CD-1). It is interesting to note that the –20dB signal
falls only about 10dB below the full scale signal instead of
the expected 20dB. This is primarily due to the superior low
level signal performance of the advanced sign magnitude
architecture of the PCM1702.
In terms of signal measurement, THD+N is the ratio of
Distortion
RMS
+ Noise
RMS
/ Signal
RMS
expressed in dB. For the
PCM1702, THD+N is 100% tested at all three specified
output levels using the test setup shown in Figure 1. It is
significant to note that this test setup does not include any
output deglitching circuitry. All specifications are achieved
without the use of external deglitchers.
Dynamic Range
Dynamic range in audio converters is specified as the mea-
sure of THD+N at an effective output signal level of –60dB
referred to 0dB. Resolution is commonly used as a theoreti-
cal measure of dynamic range, but it does not take into
account the effects of distortion and noise at low signal
levels. The advanced sign magnitude architecture of the
PCM1702, with its ideal performance around bipolar zero,
provides a more usable dynamic range, even using the strict
audio definition, than any previously available D/A con-
verter.
LOWER DAC CODE
(19-bit Straight Binary)
111...111+1LSB
(1)
111...111+1LSB
(1)
111...111+1LSB
(1)
111...111+1LSB
(1)
111...111+1LSB
(1)
111...111
111...110
000...001
000...000
UPPER DAC CODE
(19-bit Straight Binary)
111...111
111...110
000...010
000...001
000...000
000...000
000...000
000...000
000...000
ANALOG OUTPUT
+Full Scale
+Full Scale –1LSB
Bipolar Zero +2LSB
Bipolar Zero +1LSB
Bipolar Zero
Bipolar Zero –1LSB
Bipolar Zero –2LSB
–Full Scale +LSB
–Full Scale
INPUT CODE
(20-bit Binary Two's Complement)
011...111
011...110
000...010
000...001
000...000
111...111
111...110
100...001
100...000
NOTE: (1) The extra weight of 1LSB is added at this point to make the transfer function symmetrical around bipolar zero.
TABLE I. Binary Two's Complement to Sign Magnitude Conversion Chart.
®
5
PCM1702
Programming Basics
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