Features ..................................................................................................................................................................................1
5.0 x 3.2 mm Package Pinout ..................................................................................................................................................1
Modes of Operation and Pin-outs.............................................................................................................................................6
Pin-out Top Views ............................................................................................................................................................ 6
Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs .........................................................................................7
Frequency Stability ......................................................................................................................................................... 11
Output frequency and format .......................................................................................................................................... 11
Output Frequency Tuning ............................................................................................................................................... 11
Pin 1 Configuration (OE, VC, or NC) ............................................................................................................................... 12
Control Voltage Bandwidth ............................................................................................................................................. 15
Pull Range, Absolute Pull Range ........................................................................................................................................... 16
I C Control Registers ............................................................................................................................................................. 21
Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ........................................................... 21
Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ........................................ 22
Register Address: 0x02. DIGITAL PULL RANGE CONTROL .......................................................................................... 23
Register Address: 0x05. PULL-UP DRIVE STRENGTH CONTROL ................................................................................ 24
Register Address: 0x06. PULL-DOWN DRIVE STRENGTH CONTROL .......................................................................... 25
Serial Interface Configuration Description .............................................................................................................................. 26
Serial Signal Format .............................................................................................................................................................. 26
Parallel Signal Format ........................................................................................................................................................... 27
Parallel Data Format.............................................................................................................................................................. 27
I C Timing Specification......................................................................................................................................................... 29
I C Device Address Modes .................................................................................................................................................... 30
Dimensions and Patterns....................................................................................................................................................... 32
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[i=s]This post was last edited by dontium on 2015-1-23 12:51[/i] It’s so strange... The gate is driven and the duty cycle is 50%, so why are the D and S pole voltages almost always equal?...
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Microcontroller MCU
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