Philips Semiconductors
Preliminary specification
8-bit CMOS (low voltage, low power
and high speed) microcontroller families
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
DESCRIPTION
Three different Single-Chip 8-Bit Microcontroller families are
presented in this datasheet:
FEATURES
•
80C32/8XC52/8XC54/8XC58
•
80C51FA/8XC51FA/8XC51FB/8XC51FC
•
80C51RA+/8XC51RA+/8XC51RB+/8XC51RC+/8XC51RD+
For applications requiring 4K ROM/EPROM, see the 8XC51/80C31
8-bit CMOS (low voltage, low power, and high speed)
microcontroller families datasheet.
All the families are Single-Chip 8-Bit Microcontrollers manufactured
in advanced CMOS process and are derivatives of the 80C51
microcontroller family. All the devices have the same instruction set
as the 80C51.
These devices provide architectural enhancements that make them
applicable in a variety of applications for general control systems.
ROM/EPROM
Memory Size
(X by 8)
80C31/8XC51
0K/4K
80C32/8XC52/54/58
0K/8K/16K/32K
256
No
No
128
No
No
RAM Size
(X by 8)
Programmable
Timer Counter
(PCA)
Hardware
Watch Dog
Timer
•
80C51 Central Processing Unit
•
Speed up to 33MHz
•
Full static operation
•
Operating voltage range: 2.7V to 5.5V @ 16MHz
•
Security bits:
–
ROM – 2 bits
–
OTP–EPROM – 3 bits
•
Encryption array – 64 bytes
•
RAM expandable to 64K bytes
•
4 level priority interrupt
•
6 or7 interrupt sources, depending on device
•
Four 8-bit I/O ports
•
Full-duplex enhanced UART
–
Framing error detection
–
Automatic address recognition
•
Power control modes
–
Clock can be stopped and resumed
–
Idle mode
–
Power down mode
80C51FA/8XC51FA/FB/FC
0K/8K/16K/32K
256
Yes
No
80C51RA+/8XC51RA+/RB+/RC+
0K/8K/16K/32K
8XC51RD+
64K
1024
Yes
Yes
512
Yes
Yes
•
Programmable clock out
•
Second DPTR register
•
Asynchronous port reset
•
Low EMI (inhibit ALE)
The ROMless devices, 80C32, 80C51FA, and 80C51RA+ can
address up to 64K of external memory. All the devices have four
8-bit I/O ports, three 16-bit timer/event counters, a multi-source,
four-priority-level, nested interrupt structure, an enhanced UART
and on-chip oscillator and timing circuits. For systems that require
extra memory capability up to 64k bytes, each can be expanded
using standard TTL-compatible memories and logic.
Its added features make it an even more powerful microcontroller for
applications that require pulse width modulation, high-speed I/O and
up/down counting capabilities such as motor control. It also has a
more versatile serial channel that facilitates multiprocessor
communications.
1997 Dec 01
176
Philips Semiconductors
Preliminary specification
8-bit CMOS (low voltage, low power
and high speed) microcontroller families
8XC52/54/58/80C32
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
PIN DESCRIPTIONS
PIN NUMBER
MNEMONIC
V
SS
V
CC
P0.0–0.7
DIP
20
40
39–32
LCC
22
44
43–36
QFP
16
38
37–30
TYPE
I
I
I/O
NAME AND FUNCTION
Ground:
0V reference.
Power Supply:
This is the power supply voltage for normal, idle, and power-down operation.
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the
code bytes during program verification and received code bytes during EPROM
programming. External pull-ups are required during program verification.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 1 pins that are externally pulled low will source current because of the internal pull-ups.
(See DC Electrical Characteristics: I
IL
). Port 1 also receives the low-order address byte
during program memory verification.
Alternate functions for 8XC51FX and 8XC51RX+ Port 1 include:
T2 (P1.0):
Timer/Counter 2 external count input/Clockout (see Programmable Clock-Out)
T2EX (P1.1):
Timer/Counter 2 Reload/Capture/Direction Control
ECI (P1.2):
External Clock Input to the PCA
CEX0 (P1.3):
Capture/Compare External I/O for PCA module 0
CEX1 (P1.4):
Capture/Compare External I/O for PCA module 1
CEX2 (P1.5):
Capture/Compare External I/O for PCA module 2
CEX3 (P1.6):
Capture/Compare External I/O for PCA module 3
CEX4 (P1.7):
Capture/Compare External I/O for PCA module 4
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 2 pins that are externally being pulled low will source current because of the internal
pull-ups. (See DC Electrical Characteristics: I
IL
). Port 2 emits the high-order address byte
during fetches from external program memory and during accesses to external data memory
that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal
pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses
(MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins
receive the high order address bits during EPROM programming and verification.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
port 3 pins that are externally being pulled low will source current because of the pull-ups.
(See DC Electrical Characteristics: I
IL
). Port 3 also serves the special features of the 80C51
family, as listed below:
RxD (P3.0):
Serial input port
TxD (P3.1):
Serial output port
INT0 (P3.2):
External interrupt
INT1 (P3.3):
External interrupt
T0 (P3.4):
Timer 0 external input
T1 (P3.5):
Timer 1 external input
WR (P3.6):
External data memory write strobe
RD (P3.7):
External data memory read strobe
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to V
SS
permits a power-on reset using only an external
capacitor to V
CC
.
Address Latch Enable/Program Pulse:
Output pulse for latching the low byte of the
address during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data memory. This pin is
also the program pulse input (PROG) during EPROM programming. ALE can be disabled by
setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction.
P1.0–P1.7
1–8
2–9
40–44,
1–3
I/O
1
2
3
4
5
6
7
8
P2.0–P2.7
21–28
2
3
4
5
6
7
8
9
24–31
40
41
42
43
44
1
2
3
18–25
I/O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
P3.0–P3.7
10–17
11,
13–19
5,
7–13
I/O
10
11
12
13
14
15
16
17
RST
9
11
13
14
15
16
17
18
19
10
5
7
8
9
10
11
12
13
4
I
O
I
I
I
I
O
O
I
ALE/PROG
30
33
27
O
1997 Dec 01
179
FPGA/CPLD
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