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2SK656

Description
Silicon N-Channel MOS FET
CategoryDiscrete semiconductor    The transistor   
File Size30KB,2 Pages
ManufacturerPanasonic
Websitehttp://www.panasonic.co.jp/semicon/e-index.html
Download Datasheet Parametric View All

2SK656 Overview

Silicon N-Channel MOS FET

2SK656 Parametric

Parameter NameAttribute value
Parts packaging codeSC-72
package instructionIN-LINE, R-PSIP-T3
Contacts3
Reach Compliance Codeunknow
ECCN codeEAR99
Other featuresBUILT-IN BIAS RESISTOR RATIO IS 0.02, HIGH INPUT IMPEDANCE
ConfigurationSINGLE WITH BUILT-IN DIODE AND RESISTOR
Minimum drain-source breakdown voltage50 V
Maximum drain current (Abs) (ID)0.1 A
Maximum drain current (ID)0.1 A
Maximum drain-source on-resistance50 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PSIP-T3
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formIN-LINE
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)0.2 W
Certification statusNot Qualified
surface mountNO
Terminal formTHROUGH-HOLE
Terminal locationSINGLE
transistor applicationsSWITCHING
Transistor component materialsSILICON
Base Number Matches1
Silicon MOS FETs (Small Signal)
2SK656
Silicon N-Channel MOS FET
For switching
unit: mm
4.0±0.2
3.0±0.2
0.7±0.1
s
Features
q
High-speed switching
q
Small drive current owing to high input inpedance
q
High electrostatic breakdown voltage
Parameter
Drain to Source breakdown voltage
Gate to Source voltage
Drain current
Max drain current
Allowable power dissipation
Channel temperature
Storage temperature
Symbol
V
DSS
V
GSO
I
D
I
DP
P
D
T
ch
T
stg
Ratings
50
8
100
200
200
150
−55
to +150
Unit
V
V
mA
mA
mW
°C
°C
1
2
3
1.27 1.27
1: Source
2: Drain
2.54±0.15
3: Gate
EIAJ: SC-72
New S Type Package
Internal Connection
D
R
1
G
R
2
S
s
Electrical Characteristics
(Ta = 25°C)
Parameter
Drain to Source cut-off current
Gate to Source leakage current
Drain to Source breakdown voltage
Gate threshold voltage
Drain to Source ON-resistance
Forward transfer admittance
High level output voltage
Low level output voltage
Input resistance
Symbol
I
DSS
I
GSS
V
DSS
V
th
R
DS(on)
| Y
fs
|
V
OH
V
OL
R
1
+ R
2*1
C
oss
t
on*2
t
off*2
V
DS
= 10V, V
GS
= 0, f = 1MHz
V
DD
= 5V, V
GS
= 0 to 5V, R
L
= 200Ω
V
DD
= 5V, V
GS
= 5 to 0V, R
L
= 200Ω
Conditions
V
DS
= 10V, V
GS
= 0
V
GS
= 8V, V
DS
= 0
I
D
= 100µA, V
GS
= 0
I
D
= 100µA, V
DS
= V
GS
I
D
= 20mA, V
GS
= 5V
I
D
= 20mA, V
DS
= 5V, f = 1kHz
V
DD
= 5V, V
GS
= 1V, R
L
= 200Ω
V
DD
= 5V, V
GS
= 5V, R
L
= 200Ω
100
9
4.5
1.1
1
1
20
4.5
1
200
35
40
50
1.5
3.5
50
min
typ
max
10
80
Unit
µA
µA
V
V
mS
V
V
kΩ
pF
pF
pF
µs
µs
Input capacitance (Common Source) C
iss
Output capacitance (Common Source)
Reverse transfer capacitance (Common Source) C
rss
Turn-on time
Turn-off time
*1
*2
Resistance ratio R
1
/R
2
= 1/50
Pulse measurement
2.0±0.2
s
Absolute Maximum Ratings
(Ta = 25°C)
marking
+0.2
0.45–0.1
15.6±0.5
1

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