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P4C422-12DC

Description
HIGH SPEED 256 x 4 STATIC CMOS RAM
Categorystorage    storage   
File Size208KB,10 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C422-12DC Overview

HIGH SPEED 256 x 4 STATIC CMOS RAM

P4C422-12DC Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPyramid Semiconductor Corporation
Parts packaging codeDIP
package instructionDIP,
Contacts22
Reach Compliance Codecompli
ECCN codeEAR99
Maximum access time12 ns
JESD-30 codeR-CDIP-T22
JESD-609 codee0
length27.2542 mm
memory density1024 bi
Memory IC TypeSTANDARD SRAM
memory width4
Number of functions1
Number of terminals22
word count256 words
character code256
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize256X4
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height5.715 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
P4C422
HIGH SPEED 256 x 4
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35 ns (Commercial)
– 15/20/25/35 ns (Military)
CMOS for Low Power
– 495 mW Max. – 10/12/15/20/25 (Commercial)
– 495 mW Max. – 15/20/25/35 (Military)
Single 5V±10% Power Supply
Separate I/O
Fully TTL Compatible Inputs and Outputs
Resistant to single event upset and latchup
resulting from advanced process and design
improvements
Standard 22-pin 400 mil DIP, 24-pin 300 mil
SOIC, 24-pin square LCC package and 24-pin
CERPACK package
DESCRIPTION
The P4C422 is a 1,024-bit high-speed (10ns) Static
RAM with a 256 x 4 organization. The memory requires
no clocks or refreshing and has equal access and cycle
times. Inputs and outputs are fully TTL compatible.
Operation is from a single 5 Volt supply. Easy memory
expansion is provided by an active LOW chip select one
(CS
1
) and active HIGH chip select two (CS
2
) as well as
3-state outputs.
In addition to high performance and high density, the
device features latch-up protection, single event and
upset protection. The P4C422 is offered in several
packages: 22-pin 400 mil DIP (plastic and ceramic), 24-
pin 300 mil SOIC, 24-pin square LCC and 24-pin
CERPACK. Devices are offered in both commercial and
military temperature ranges.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
SOIC (S4)
CERPACK (F3) SIMILAR
DIP (P3-1, C3-1, D3-1)
LCC (L4)
Document #
SRAM101
REV. A
1
Revised October 2005
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