P4C422
HIGH SPEED 256 x 4
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35 ns (Commercial)
– 15/20/25/35 ns (Military)
CMOS for Low Power
– 495 mW Max. – 10/12/15/20/25 (Commercial)
– 495 mW Max. – 15/20/25/35 (Military)
Single 5V±10% Power Supply
Separate I/O
Fully TTL Compatible Inputs and Outputs
Resistant to single event upset and latchup
resulting from advanced process and design
improvements
Standard 22-pin 400 mil DIP, 24-pin 300 mil
SOIC, 24-pin square LCC package and 24-pin
CERPACK package
DESCRIPTION
The P4C422 is a 1,024-bit high-speed (10ns) Static
RAM with a 256 x 4 organization. The memory requires
no clocks or refreshing and has equal access and cycle
times. Inputs and outputs are fully TTL compatible.
Operation is from a single 5 Volt supply. Easy memory
expansion is provided by an active LOW chip select one
(CS
1
) and active HIGH chip select two (CS
2
) as well as
3-state outputs.
In addition to high performance and high density, the
device features latch-up protection, single event and
upset protection. The P4C422 is offered in several
packages: 22-pin 400 mil DIP (plastic and ceramic), 24-
pin 300 mil SOIC, 24-pin square LCC and 24-pin
CERPACK. Devices are offered in both commercial and
military temperature ranges.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
SOIC (S4)
CERPACK (F3) SIMILAR
DIP (P3-1, C3-1, D3-1)
LCC (L4)
Document #
SRAM101
REV. A
1
Revised October 2005
P4C422
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
– 0.5 to +7
– 0.5 to
V
CC
+0.5
– 55 to +125
Unit
V
Symbol
T
BIAS
T
STG
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
DC Output Current
Value
– 55 to +125
– 65 to +150
20
Unit
°C
°C
mA
V
TERM
T
A
V
°C
RECOMMENDED OPERATING CONDITIONS
Grade
(2)
Commercial
Military
Ambient Temp
0°C to 70°C
–55°C to 125°C
Gnd
0V
0V
Vcc
5.0V ±10%
5.0V ±10%
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Conditions Typ. Unit
V
IN
= 0V
5
7
pF
pF
Output Capacitance V
OUT
= 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
OH
V
OL
V
IH
V
IL
V
CL
I
IX
I
OZ
I
OS
Parameter
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Clamp Diode Voltage
Input Load Current
Output Current (High Z)
Output Short Circuit
Current
(3)
Test Conditions
I
OH
= –5.2 mA, V
CC
= Min.2.4
I
OL
= +8 mA, V
CC
= Min.
P4C422
Min
Max
V
0.4
2.1
0.8
Unit
V
V
V
V
µA
µA
mA
I
IN
= –10 mA
GND
≤
V
IN
≤
V
CC
V
OL
≤
V
OUT
≤
V
OH
, Output Disabled
V
CC
= Max., V
OUT
= GND
–1.5
–10
–10
10
10
90
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
I
CC
Parameter
Dynamic Operating Current
Temperature
Range
Commercial
Military
-10
90
N/A
-12
90
N/A
-15
90
90
-20
90
90
-25
65
90
-35
65
90
Unit
mA
mA
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. For test purposes, not more than one output at a time should be
shorted. Short circuit test duration should not exceed 30 seconds.
4. This parameter is sampled and not 100% tested.
5. Transition time is
≤
3ns for 10, 12, and 15 ns products and
≤
5ns for
20, 25, and 35 ns products, see Fig 1d. Timing is referenced at input
and output levels of 1.5V. The output loading is equivalent to the
specified I
OL
/I
OH
with a load capacitance of 15 pF (10, 12) or 30 pF (15,
20, 25, 35) as in Fig. 1a and 1b respectively.
6. Transition time is
≤
3ns for 10, 12, and 15 ns products and
≤
5ns for
20, 25, and 35 ns products, see Fig 1d. Transition is measured at
steady state HIGH level -500mV or steady state LOW level +500mV
on the output from a level on the input with load shown in Fig. 1c.
7. t
W
is measured at t
WSA
= min.; t
WSA
is measured at t
W
= min.
Document #
SRAM101
REV. A
Page 2 of 10
P4C422
FUNCTIONAL DESCRIPTION
An active LOW write enable (WE) controls the writing/
reading operation of the memory. When the chip select
one (CS
1
) and the write enable (WE) are LOW and the chip
select two (CS
2
) is HIGH, the information on data inputs
(D
0
through D
3
) is written into the addressed memory word
and preconditions the output circuitry so that true data is
present at the outputs when the write cycle is complete.
This preconditioning operation insures minimum write
recovery times by eliminating the “write recovery glitch.”
Reading is performed with chip selct one (CS
1
) LOW, chip
select two (CS
2
) HIGH, write enable (WE) HIGH and
output enable (OE) LOW. The information stored in the
addressed word is read out on the noninverting outputs
(O
0
through O
3
). The outputs of the memory go to an
inactive high impedance state whenever chip select one
(CS
1
) is HIGH, or during the write operation when write
enable (WE) is LOW.
TRUTH TABLE
Mode
Standby
Standby
D
OUT
Disabled
Read
Write
CS
2
L
X
H
H
H
CS
1
X
H
L
L
L
WE
X
X
X
H
L
OE
X
X
H
L
X
Output
High Z
High Z
High Z
D
OUT
High Z
Notes:
H
L
X
HIGH Z
= HIGH
= Low
= Don't Care
= Implies outputs are disabled or off. This condition
is defined as high impedance state for the
P4C422.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10% except as noted, All Temperature Ranges)
(2)
Sym.
t
RC
t
ACS
t
ZRCS
t
AOS
t
ZROS
t
AA
Parameter
Read Cycle Time
(5)
Chip Select Time
(5)
Chip Select to High-Z
(6)
Output Enable Time
Output Enable to High-Z
(6)
Address Access Time
(5)
-10*
12
7.5
8
7.5
8
10
-12
-15
15
8
8
12
8
12
15
-20
20
12
15
12
15
20
-25
-35
35
Min Max Min Max Min Max Min Max Min Max Min Max
12
25
15
20
15
20
25
25
30
25
30
35
Unit
ns
ns
ns
ns
ns
ns
10
8
10
12
*V
CC
= 5V ± 5%
TIMING WAVEFORM OF READ CYCLE
Document #
SRAM101
REV. A
Page 3 of 10
P4C422
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10% except as noted, All Temperature Ranges)
(2)
Sym.
t
WC
t
ZWS
t
WR
t
W
t
WSD
t
WHD
t
WSA
t
WHA
t
WSCS
t
WHCS
Parameter
Write Cycle Time
(5)
Write Enable to High-Z
(6)
Write Recovery Time
Write Pulse Width
(5,7)
Data Setup Time Prior to Write
(5)
Data Hold Time
(5)
Address Setup Time
(5,7)
Address Hold Time
(5)
Chip Select Setup Time
(5)
Chip Select Hold Time
(5)
8
-10*
10
8
8
9
0
2
0
2
0
2
12
-12
15
10
10
11
0
2
0
4
0
2
-15
-20
20
-25
25
35
20
20
15
5
5
5
5
5
5
20
5
5
5
5
5
5
-35
Min Max Min Max Min Max Min Max Min Max Min Max
12
12
13
2
5
2
5
2
5
15
15
30
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
2
0
2
0
2
*V
CC
= 5V ± 5%
TIMING WAVEFORM OF WRITE CYCLE
Document #
SRAM101
REV. A
Page 4 of 10
P4C422
AC TEST LOADS & WAVEFORMS
Figure 1a
Figure 1b
Figure 1c
Figure 1d
Document #
SRAM101
REV. A
Page 5 of 10
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