P4C187-10PC datasheet, PDF - EEWORLD Datasheet

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P4C187-10PC: DescriptionULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS; Categorystorage storage; File Size311KB，12 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P4C187-10PC Overview

ULTRA HIGH SPEED 64K x 1 STATIC CMOS RAMS

P4C187-10PC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	DIP
package instruction	DIP, DIP22,.3
Contacts	22
Reach Compliance Code	compli
ECCN code	EAR99
Maximum access time	10 ns
I/O type	SEPARATE
JESD-30 code	R-PDIP-T22
JESD-609 code	e0
length	29.337 mm
memory density	65536 bi
Memory IC Type	STANDARD SRAM
memory width	1
Number of functions	1
Number of terminals	22
word count	65536 words
character code	64000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX1
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP22,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	5.334 mm
Maximum standby current	0.015 A
Minimum standby current	4.5 V
Maximum slew rate	0.18 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

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P4C187/P4C187L

ULTRA HIGH SPEED 64K x 1

STATIC CMOS RAMS

FEATURES

Full CMOS, 6T Cell

High Speed (Equal Access and Cycle Times)

– 10/12/15/20/25/35/45 ns (Commercial)

– 12/15/20/25/35 /45 ns (Industrial)

– 15/20/25/35/45/55/70/85 ns (Military)

Low Power Operation

– 743 mW Active -10

– 660/770 mW Active for -12/15

– 550/660 mW Active for -20/25/35

– 193/220 mW Standby (TTL Input)

– 83/110 mW Standby (CMOS Input) P4C187

– 5.5 mW Standby (CMOS Input) P4C187L (Military)

Single 5V±10% Power Supply

Data Retention with 2.0V Supply (P4C187L

Military)

Separate Data I/O

Three-State Output

TTL Compatible Output

Fully TTL Compatible Inputs

Standard Pinout (JEDEC Approved)

– 22-Pin 300 mil DIP

– 24-Pin 300 mil SOJ

– 22-Pin 290x490 mil LCC

– 28-Pin 350x550 mil LCC

DESCRIPTION

The P4C187/P4C187L are 65, 536-bit ultra high speed

static RAMs organized as 64K x 1. The CMOS memories

require no clocks or refreshing and have equal access and

cycle times. The RAMs operate from a single 5V ± 10%

tolerance power supply. Data integrity is maintained for sup-

ply voltages down to 2.0V, typically drawing 10µA.

Access times as fast as 10 nanoseconds are available,

greatly enhancing system speeds. CMOS reduces power

consumption to a low 743mW active, 193/83mW standby

for TTL/CMOS inputs and only 5.5 mW standby for the

P4C187L.

The P4C187/P4C187L are available in 22-pin 300 mil DIP,

24-pin 300 mil SOJ, 22-pin and 28-pin LCC packages pro-

viding excellent board level densities.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

DIP (P3, D3, C3)

SOJ (J4)

LCC Pin configurations at end of datasheet.

Document #

SRAM111

REV B

Revised April 2007

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