P4C174
HIGH SPEED 8K x 8
CACHE TAG STATIC RAM
FEATURES
High Speed Address-To-Match - 8 ns Maximum
Access Time
High-Speed Read-Access Time
– 8/10/12/15/20/25 ns (Commercial)
– 15/20/25 ns (Military)
Open Drain MATCH Output
Reset Function
8-Bit Tag Comparison Logic
Automatic Powerdown During Long Cycles
Data Retention at 2V for Battery Backup
Operation
Advanced CMOS Technology
Low Power Operation
Package Styles Available
— 28 Pin 300 mil DIP
— 28 Pin 300 mil Plastic SOJ
Single Power Supply
— 5V±10%
DESCRIPTION
The P4C174 is a 65,536 bit high speed cache tag static
RAM organized as 8K x 8. The CMOS memory has equal
access and cycle times. Inputs are fully TTL-compatible.
The cache tag RAMs operate from a single 5V±10%
power supply. An 8-bit data comparator with a MATCH
output is included for use as an address tag comparator
in high speed cache applications. The reset function
provides the capability to reset all memory locations to a
LOW level.
The MATCH output of the P4C174 reflects the compari-
son result between the 8-bit data on the I/O pins and
the addressed memory location. 8K Cache lines can be
mapped into 1M-Byte address spaces by comparing 20
address bits organized as 13-line address bits and 7-
page address bits.
Low power operation of the P4C174 is enhanced by
automatic powerdown when the memory is deselected or
during long cycle times. Also, data retention is main-
tained down to V
CC
= 2.0. Typical battery backup appli-
cations consume only 30
µ
W at V
CC
=
3.0V.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (C5, P5), SOJ (J5)
Document #
SRAM118
REV C
1
Revised August 2006
P4C174
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
V
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Commercial
Commercial
Ambient
Temperature
0°C to +70°C
0°C to +70°C
GND
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Conditions Typ. Unit
V
IN
= 0V
V
OUT
= 0V
5
7
pF
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
I
SB
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage V
CC
= Min., I
IN
= 18 mA
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
I
OL
= +8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.,
CE
= V
IH
,
V
OUT
= GND to V
CC
Com’l.
Mil.
Com’l.
Mil.
2.4
–5
-10
–5
-10
___
___
___
___
+5
+10
+5
+10
25
40
5
25
mA
Test Conditions
P4C174
Min
Max
2.2
–0.5
(3)
–0.5
(3)
V
CC
+0.5
0.8
0.2
–1.2
0.4
Unit
V
V
V
V
V
V
V
µA
µA
V
CC
–0.2 V
CC
+0.5
CE
≥
V
IH
Com’l.
Standby Power Supply
Mil.
Current (TTL Input Levels) V
CC
= Max .,
f = Max., Outputs Open
Standby Power Supply
Current
(CMOS Input Levels)
CE
≥
V
HC
V
CC
= Max.,
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
Com’l.
Mil.
I
SB1
mA
n/a = Not Applicable
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Document #
SRAM118
REV C
Page 2 of 12
P4C174
DATA RETENTION CHARACTERISTICS (P4C174 Military Temperature Only)
Symbol
V
DR
I
CCDR
t
CDR
t
R†
*T
A
= +25¹C
§t
RC
= Read Cycle Time
†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Test Conditons
Min
2.0
Typ.*
V
CC
=
2.0V
3.0V
Max
V
CC
=
2.0V
3.0V
Unit
V
CE
≥
V
CC
–0.2V,
V
IN
≥
V
CC
–0.2V
or V
IN
≤
0.2V
0
t
RC§
10
15
600
900
µA
ns
ns
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
I
CC
Parameter
Dynamic Operating Current*
Temperature
Range
Commercial
Military
–8
200
–10
180
–12
170
170
–15
–20
155
160
–25
150
155
Unit
mA
mA
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
,
OE
= V
IH
.
Document #
SRAM118
REV C
Page 3 of 12
P4C174
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Symbol
t
RC
t
AA
t
OH
t
AC
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
Parameter
Read Cycle Time
Address Access
Time
Address Change to
Output Change
Chip Enable LOW to
Output Valid
Chip Enable LOW
to Output LOW-Z
(1)
Chip Enable HIGH
to Output HIGH -Z
(1)
Output Enable LOW
to Output Valid
Output Enable LOW
to Output LOW-Z
(1)
Output Enable HIGH
to Output HIGH -Z
(1)
Chip Enable LOW or
Address Change to
Powerup
Powerup to
Powerdown
–8
Min Max
8
8
3
8
3
5
5
0
5
0
0
0
3
3
10
–10
12
10
3
10
3
5
6
0
5
0
–12
Max
12
3
12
3
5
6
0
5
0
15
–15
Min Max
15
3
15
3
8
8
0
5
0
20
–20
Min
25
20
3
20
3
8
10
0
8
0
–25
Min Max Min
Max Min Max
25
Unit
ns
ns
ns
25
ns
ns
10
12
ns
ns
ns
10
ns
ns
t
pUPD
20
20
20
20
20
25
ns
Note:
1. Transition is measured ± 200 mV from steady state voltage with Output Load B.
READ CYCLE NO. 1 (OE CONTROLLED)
(2, 3)
OE
Document #
SRAM118
REV C
Page 4 of 12
P4C174
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(2)
READ CYCLE NO. 3 (CE CONTROLLED)
(2, 3)
CE
Notes:
1. Transition is measured ±200 mV from steady state voltage with
Output
Load B. This parameter is sampled, not 100% tested.
2.
CE
is LOW,
OE
is LOW,
WE
is HIGH for READ cycle.
CE
or
WE
must
be HIGH during address transitions.
3. All address lines are valid no later than the transition of
CE
to LOW.
4. READ cycle time is measured from the last valid address to the first
transitioning address.
5. Powerup occurs as a result of any of the following conditions:
a) Falling edge of
CE.
b) Falling edge of
WE
(CE active).
c) Any address line transition (CE active).
d) Any Data line transition (CE and
WE
active).
This device automatically powers down after T
PUPD
has elapsed from
any of the prior conditions. Power dissipation is therefore a function
of cycle rate, not
CE
pulse width.
6.
CE
is LOW,
WE
is LOW for WRITE cycle.
CE
or
WE
must be HIGH
during address transitions.
7. WRITE cycle time is measured from the last valid address to the first
transitioning address.
8.
OE
is LOW for this WRITE cycle to show T
WZ
and T
OW
.
Document #
SRAM118
REV C
Page 5 of 12
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