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P4C164L-80SILF

Description
LOW POWER 8K x 8 STATIC CMOS RAM
Categorystorage    storage   
File Size112KB,11 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Environmental Compliance
Download Datasheet Parametric View All

P4C164L-80SILF Overview

LOW POWER 8K x 8 STATIC CMOS RAM

P4C164L-80SILF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerPyramid Semiconductor Corporation
Parts packaging codeSOIC
package instructionSOP,
Contacts28
Reach Compliance Codecompliant
ECCN codeEAR99
Maximum access time80 ns
JESD-30 codeR-PDSO-G28
JESD-609 codee3
length18.0086 mm
memory density65536 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals28
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize8KX8
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height2.5908 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width8.5979 mm
Base Number Matches1
P4C164L
LOW POWER 8K x 8
STATIC CMOS RAM
FEATURES
V
CC
Current (Commercial/Industrial)
— Operating: 55 mA
— CMOS Standby: 3 µA
Access Times
—80/100 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE
1
, CE
2
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin 300 and 600 mil DIP
—28-Pin 330 mil SOP
DESCRIPTION
The P4C164L is a 64K density low power CMOS
static RAM organized as 8Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 80 ns and 100 ns are available. CMOS
is utilized to reduce power consumption to a low level.
The P4C164L device provides asynchronous operation
with matching access and cycle times.
Memory locations are specified on address pins A
0
to
A
12
. Reading is accomplished by device selection (CE
1
low CE
2
high) and output enabling (OE) while write en-
able (WE) remains HIGH. By presenting the address
under these conditions, the data in the addressed memory
location is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
Package options for the P4C164L include 28-pin 300 and
600 mil DIP and 28-pin 330 mil SOP packages.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P5, P6), SOP (S5)
TOP VIEW
Document #
SRAM116
REV B
Revised June 2007
1
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