P4C164L
LOW POWER 8K x 8
STATIC CMOS RAM
FEATURES
V
CC
Current (Commercial/Industrial)
— Operating: 55 mA
— CMOS Standby: 3 µA
Access Times
—80/100 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE
1
, CE
2
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin 300 and 600 mil DIP
—28-Pin 330 mil SOP
DESCRIPTION
The P4C164L is a 64K density low power CMOS
static RAM organized as 8Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 80 ns and 100 ns are available. CMOS
is utilized to reduce power consumption to a low level.
The P4C164L device provides asynchronous operation
with matching access and cycle times.
Memory locations are specified on address pins A
0
to
A
12
. Reading is accomplished by device selection (CE
1
low CE
2
high) and output enabling (OE) while write en-
able (WE) remains HIGH. By presenting the address
under these conditions, the data in the addressed memory
location is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
Package options for the P4C164L include 28-pin 300 and
600 mil DIP and 28-pin 330 mil SOP packages.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P5, P6), SOP (S5)
TOP VIEW
Document #
SRAM116
REV B
Revised June 2007
1
P4C164L
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Commercial (0°C to 70°C)
Industrial (-40°C to 85°C)
Supply Voltage
4.5V
≤
V
CC
≤
5.5V
4.5
≤
V
CC
≤
5.5V
MAXIMUM RATINGS
(1)
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings
only. Functional operation of the device is not implied at these or any other conditions in excess of those given in
the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely
affect device reliability.
Symbol
V
CC
V
TERM
T
A
S
TG
I
OUT
I
LAT
Parameter
Supply Voltage with Respect to GND
Terminal Voltage with Respect to GND (up to 7.0V)
Operating Ambient Temperature
Storage Temperature
Output Current into Low Outputs
Latch-up Current
>200
Min
-0.5
-0.5
-55
-65
Max
7.0
V
CC
+ 0.5
125
150
25
Unit
V
V
°C
°C
mA
mA
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
SB
Parameter
Output High Voltage
(I/O
0
- I/O
7
)
Output Low Voltage
(I/O
0
- I/O
7
)
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
V
CC
Current
TTL Standby Current
(TTL Input Levels)
V
CC
Current
CMOS Standby Current
(CMOS Input Levels)
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
CE
≥
V
IH
Ind./Com.
Ind./Com.
Test Conditions
I
OH
= –1mA, V
CC
= 4.5V
I
OL
= 2.1mA
2.2
-0.5
(3)
-2
-2
Min
2.4
0.4
V
CC
+ 0.3
0.8
+2
+2
Max
Unit
V
V
V
V
µA
µA
V
CC
= 5.5V, I
OUT
= 0 mA
CE
1
= V
IH
or CE
2
= V
IL
V
CC
= 5.5V, I
OUT
= 0 mA
CE
1
≥
V
CC
-0.2V or CE
2
≤
0.2V
100
µA
I
SB1
3
µA
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Document #
SRAM116
REV B
Page 2 of 11
P4C164L
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25°C, F = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Max
7
9
Unit
pF
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
I
CC
Parameter
Dynamic Operating Current
Temperature Range
Ind. & Comm.
*
-80
55
-100
55
Unit
mA
*Tested
with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e.
CE
and
WE
≤
V
IL
(max),
OE
is high. Switching
inputs are 0V and 3V.
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
-80
Min
80
80
80
10
10
30
10
10
30
Max
Min
100
100
100
-100
Max
Symbol
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable Low
to Data Valid
Output Enable Low to
Low Z
Output Enable High
to High Z
Chip Enable to Power
Up Time
Chip Disable to Power
Down Time
Unit
ns
ns
ns
ns
ns
ns
40
5
20
0
80
0
5
40
ns
ns
20
ns
ns
100
ns
Document #
SRAM116
REV B
Page 3 of 11
P4C164L
READ CYCLE NO. 1 (OE CONTROLLED)
(1)
OE
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (CE
1
,CE
2
CONTROLLED)
CE
NOTES:
Notes:
5.
WE
is HIGH for READ cycle.
6.
CE
1
is LOW, CE
2
is HIGH and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
1
transition LOW
and CE
2
transition HIGH.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether
CE
1
or CE
2
causes them.
Document #
SRAM116
REV B
Page 4 of 11
P4C164L
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
-80
Symbol
Parameter
Min
Max
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Write Cycle Time
Chip Enable Time
to End of Write
Address Valid to
End of Write
Address Set-up
Time
Write Pulse Width
Address Hold Time
Data Valid to End
of Write
Data Hold Time
Write Enable to
Output in High Z
Output Active from
End of Write
10
80
70
70
0
60
0
40
0
30
10
-100
Min
100
80
80
0
60
0
40
0
30
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE NO. 1 (WE CONTROLLED)
(6)
WE
Notes:
11.
CE
1
and
WE
must be LOW, and CE
2
HIGH for WRITE cycle.
12.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
13. If
CE
1
goes HIGH, or CE
2
goes LOW, simultaneously with WE HIGH,
the output remains in a high impedance state.
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM116
REV B
Page 5 of 11
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