P4C164
ULTRA HIGH SPEED 8K x 8
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 8/10/12/15/20/25/35/70/100 ns (Commercial)
– 10/12/15/20/25/35/70/100 ns(Industrial)
– 12/15/20/25/35/45/70/100 ns (Military)
Low Power Operation
Output Enable and Dual Chip Enable Control
Functions
Single 5V±10% Power Supply
Data Retention with 2.0V Supply, 10 µA Typical
Current (P4C164L Military)
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil Plastic DIP, SOJ
– 28-Pin 600 mil Plastic DIP (70 & 100ns)
– 28-Pin 300 mil SOP (70 & 100ns)
– 28-Pin 300 mil Ceramic DIP
– 28-Pin 600 mil Ceramic DIP
– 28-Pin 350 x 550 mil LCC
– 32-Pin 450 x 550 mil LCC
– 28-Pin CERPACK
DESCRIPTION
The P4C164 is a 65,536-bit ultra high-speed static RAM
organized as 8K x 8. The CMOS memory requires no
clocks or refreshing and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply. With
battery backup, data integrity is maintained with supply
voltages down to 2.0V. Current drain is typically 10 µA
from a 2.0V supply.
Access times as fast as 8 nanoseconds are available,
permitting greatly enhanced system operating speeds.
The P4C164 is available in 28-pin 300 mil DIP and SOJ, 28-
pin 600 mil plastic and ceramic DIP, 28-pin 350 x 550 mil
LCC, 32-pin 450 x 550 mil LCC, and 28-pin CERPACK.
The 70ns and 100ns P4C164s are available in the 600 mil
plastic DIP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P5, P6, C5, C5-1, D5-1, D5-2),
SOJ (J5), CERPACK (F4), SOP(S6)
SEE PAGE 7 FOR LCC PIN CONFIGURATIONS
1519B
Document #
SRAM115
REV F
Revised June 2007
1
P4C164
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
V
°C
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
(2)
Military
Ambient
Temperature
GND
0V
0V
0V
V
CC
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Conditions Typ. Unit
V
IN
= 0V
5
7
pF
pF
–55°C to +125°C
–40°C to +85°C
Industrial
Commercial
0°C to +70°C
Output Capacitance V
OUT
= 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage V
CC
= Min., I
IN
= –18 mA
Output Low Voltage
I
OL
= +8 mA, V
CC
= Min.
(TTL Load)
Output High Voltage
I
OH
= –4 mA, V
CC
= Min.
(TTL Load)
V
CC
= Max.
Mil.
Input Leakage Current
V
IN
= GND to V
CC
Ind./Com’l.
Output Leakage Current
V
CC
= Max.,
CE
= V
IH
,
V
OUT
= GND to V
CC
Mil.
Ind./Com’l.
Test Conditions
P4C164
Min
Max
V
CC
+0.5
2.2
–0.5
(3)
–0.5
(3)
0.8
0.2
–1.2
0.4
2.4
–10
–5
–10
–5
___
___
+10
+5
+10
+5
40
30
2.4
–5
n/a
–5
n/a
___
___
+5
n/a
+5
n/a
40
n/a
P4C164L
Unit
Min
Max
2.2
V
CC
+0.5 V
–0.5
(3)
–0.5
(3)
0.8
0.2
–1.2
0.4
V
V
V
V
V
V
µA
µA
mA
V
CC
–0.2 V
CC
+0.5 V
CC
–0.2 V
CC
+0.5
I
SB
Standby Power Supply
Current (TTL Input Levels)
CE
1
≥
V
IH
or
Mil.
CE
2
≤V
IL
,
Ind./Com’l.
V
CC
= Max,
f = Max., Outputs Open
CE
1
≥
V
HC
or
Mil.
CE
2
≤V
LC
,
Ind./Com’l.
V
CC
= Max,
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
I
SB1
Standby Power Supply
Current
(CMOS Input Levels)
___
___
25
15
___
___
1
n/a
mA
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Document #
SRAM115
REV F
Page 2 of 16
P4C164
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature
Range
Commercial
I
CC
Dynamic Operating Current* Industrial
Military
-8
-10
-12
-15
-20
-25
-35
45
-70 -100
Unit
mA
mA
mA
200 180 170 160 155 150 145 N/A 130 125
N/A 190 180 170 160 155 150 N/A 145 140
N/A N/A 180 170 160 155 150 145 145 145
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
1
= V
IL
, CE
2
= V
IH
,
OE
= V
IH
DATA RETENTION CHARACTERISTICS (P4C164L, Military Temperature Only)
Symbol
V
DR
I
CCDR
t
CDR
t
R †
*
T
A
= +25°C
§
†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Test Condition
Min
2.0
Typ.*
V
CC
=
2.0V
3.0V
10
15
Max
V
CC
=
2.0V
3.0V
200
300
Unit
V
µA
ns
ns
CE
1
≥
V
CC
– 0.2V or
CE
2
≤
0.2V, V
IN
≥
V
CC
– 0.2V
or V
IN
≤
0.2V
t
RC§
0
t
RC
= Read Cycle Time
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
Document #
SRAM115
REV F
Page 3 of 16
P4C164
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Symbol
t
RC
t
AA
t
AC
Parameter
Read Cycle
Time
Address
Access Time
Chip Enable
Access Time
Output Hold
from Address
Change
Chip Enable to
Output in Low Z
Chip Disable
to Output in
High Z
Output Enable
Low to Data
Valid
Output Enable
Low to Low Z
Output Enable
High to High Z
Chip Enable to
Power Up
Time
Chip Disable
to Power Down
Time
0
2
5
3
-8
-10
-12
-15
-20
-25
-35
-45
-70
-100
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit
8
8
8
10
10
10
12
12
12
15
15
15
20
20
20
25
25
25
35
35
35
45
45
45
70
70
70
100
100
100
ns
ns
ns
t
OH
3
3
3
3
3
3
3
3
3
ns
t
LZ
2
2
2
2
2
2
2
2
2
2
ns
t
HZ
5
6
7
8
8
10
15
20
35
45
ns
t
OE
5
6
7
9
10
13
18
20
35
45
ns
t
OLZ
t
OHZ
2
6
2
7
2
9
2
9
2
12
2
15
2
20
2
35
2
45
ns
ns
t
PU
0
0
0
0
0
0
0
0
0
ns
t
PD
8
10
12
15
20
20
20
25
35
45
ns
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)
(5)
OE
Notes:
5.
WE
is HIGH for READ cycle.
6.
CE
1
is LOW, CE
2
is HIGH and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
1
transition
LOW and CE
2
transition HIGH.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
Document #
SRAM115
REV F
Page 4 of 16
P4C164
TIMINIG WAVERFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE
1
, CE
2
CONTROLLED)
(5,7,10)
CE
Notes:
9. READ Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays
irrespective of whether
CE
1
or CE
2
causes them.
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable
Time to End of
Write
Address Valid to
End of Write
Address Set-up
Time
Write Pulse
Width
Address Hold
Time
Data Valid to
End of Write
Date Hold Time
Write Enable to
Output in High Z
Output Active
from End of
Write
3
-8
-10
-12
-15
-20
-25
-35
-45
-70
-100
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
8
6
10
7
12
8
15
12
20
15
25
18
35
25
45
33
70
50
100
70
ns
ns
7
0
7
0
6
0
6
8
0
8
0
7
0
7
10
0
9
0
8
0
7
12
0
12
0
9
0
7
15
0
15
0
11
0
8
18
0
18
0
13
0
10
25
0
20
0
15
0
14
33
0
25
0
20
0
18
50
0
40
0
30
0
30
70
0
50
0
40
0
40
ns
ns
ns
ns
ns
ns
ns
3
3
3
3
3
3
3
3
3
ns
Document #
SRAM115
REV F
Page 5 of 16
stm32/stm8
京公网安备 11010802033920号
EEWORLD
