P4C147
ULTRA HIGH SPEED 4K x 1
STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 15/20/25/35 ns (Military)
Low Power Operation
– 715 mW Active
–10 (Commercial)
– 550 mW Active
–25 (Commercial)
– 110 mW Standby (TTL Input)
– 55 mW Standby (CMOS Input)
Single 5V ± 10% Power Supply
Separate Input and Output Ports
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Standard Pinout (JEDEC Approved)
– 18 Pin 300 mil DIP
– 18 Pin CERPACK
– 18 Pin LCC (290 x 430 mils)
– 18 Pin LCC (295 x 335 mils)
DESCRIPTION
The P4C147 is a 4,096-bit ultra high speed static RAM
organized as 4K x 1. The CMOS memory requires no
clocks or refreshing, and have equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V ± 10% tolerance power supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is utilized to reduce power consumption in both
active and standby modes. In addition to very high
performance, this device features latch-up protection
and single-event-upset protection.
The P4C147 is available in 18 pin 300 mil DIP packages,
an 18-pin CERPACK package, and 2 different LCC
packages.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P1, D1, C9),
CERPACK (F1) SIMILAR
LCC (L7, L7-1)
Document #
SRAM103
REV A
1
Revised October 2005
P4C147
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
– 0.5 to +7
– 0.5 to
V
CC
+0.5
– 55 to +125
Unit
V
Symbol
T
BIAS
T
STG
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
– 55 to +125
– 65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
V
°C
RECOMMENDED OPERATING
CONDITIONS
Grade
(2)
Commercial
Military
Ambient Temp
0°C to 70°C
-55°C to +125°C
Gnd
0V
0V
V
CC
5.0V
± 10%
5.0V
± 10%
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Conditions Typ. Unit
V
IN
= 0V
5
7
pF
pF
Output Capacitance V
OUT
= 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage (2)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
SB
I
SB1
Parameter
Output High Voltage
(TTL Load)
Output Low Voltage
(TTL Load)
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Standby Power Supply
Current (TTL Input Levels)
Standby Power Supply
Current
(CMOS Input Levels)
V
CC
= Max., V
IN
= GND to V
CC
V
CC
= Max.,
CE
= V
IH
,
V
OUT
= GND to V
CC
CE
≥
V
IH
, V
CC
= Max.,
f=Max., Output Open
CE
≥
V
HC
, V
CC
= Max., f= 0,
Output Open
V
IN
≤
0.2V or V
IN
≥
V
CC
-0.2V
Mil.
Comm’l
Mil.
Comm’l
Mil.
Comm’l
Mil.
Comm’l
Test Conditions
I
OH
= –4 mA, V
CC
= Min.
I
OL
= +8 mA, V
CC
= Min
2.2
–0.5
(3)
–10
–5
–10
–5
__
__
__
__
P4C147
Min.
2.4
0.4
V
CC
=+0.5
0.8
+10
+5
+10
+5
30
23
15
10
Max.
Unit
V
V
V
V
µA
µA
mA
mA
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
I
CC
Parameter
Dynamic Operating Current
Temperature
Range
Commercial
Military
-10
130
N/A
-12
130
N/A
-15
120
145
-20
115
135
-25
100
125
-35
N/A
120
Unit
mA
mA
Document #
SRAM103
REV A
Page 2 of 10
P4C147
AC CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Chip Enable to
Power Up Time
Chip Disable to
Power Down Time
-10
10
10
10
2
2
4
0
10
0
2
2
12
-12
15
12
12
2
2
5
0
12
-15
20
15
15
2
2
6
0
15
-20
-25
25
20
20
2
2
8
0
20
25
10
0
25
25
2
2
35
-35
Min Max Min Max Min Max Min Max Min Max Min Max
35
35
Unit
ns
ns
ns
ns
ns
14
ns
ns
35
ns
TIMING WAVEFORM OF READ CYCLE NO. 1
(5)
TIMING WAVEFORM OF READ CYCLE NO. 2
(6)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
CE
is LOW and
WE
is HIGH for READ cycle.
6.
WE
is HIGH, and address must be valid prior to or coincident with
CE
transition LOW.
7. Transition is measured ±200mV from steady state voltage prior to
change with specified loading in Figure 1. This parameter is sampled
and not 100% tested.
8. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM103
REV A
Page 3 of 10
P4C147
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time from
End of Write
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
-10
-25
-12
-15
-20
-35
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
10
8
8
0
8
0
5
0
5
0
0
12
10
10
0
10
0
6
0
6
0
15
12
12
0
12
0
7
0
7
0
20
15
15
0
14
0
9
0
9
0
25
20
20
0
15
0
12
0
12
0
35
25
25
0
18
0
15
0
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(9)
WE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)
(9)
CE
Notes:
9.
CE
and
WE
must be LOW for WRITE cycle.
10. If
CE
goes HIGH simultaneously with
WE
high, the output remains
in a high impedance state.
11. Write Cycle Time is measured from the last valid address to the first
transition address.
Document #
SRAM103
REV A
Page 4 of 10
P4C147
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
TRUTH TABLE
Mode
Standby
Read
Write
CE
H
L
L
WE
X
H
L
Output
High Z
D
OUT
High Z
Power
Standby
Active
Active
Figure 1. Output Load
* including scope and test fixture.
Figure 2. Thevenin Equivalent
Note:
Due to the ultra-high speed of the P4C147, care must be taken when
testing this device; an inadequate setup can cause a normal functioning
part to be rejected as faulty. Long high-inductance leads that cause
supply bounce must be avoided by bringing the V
CC
and ground planes
directly up to the contactor fingers. A 0.01 µF high frequency capacitor
is also required between V
CC
and ground. To avoid signal reflections,
proper termination must be used; for example, a 50
Ω
test environment
should be terminated into a 50
Ω
load with 1.73V (Thevenin Voltage) at
the comparator input, and a 116
Ω
resistor must be used in series with
D
OUT
to match 166
Ω
(Thevenin Resistance).
Document #
SRAM103
REV A
Page 5 of 10
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