P4C1256-70L32M datasheet, PDF - EEWORLD Datasheet

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P4C1256-70L32M: DescriptionHIGH SPEED 32K x 8 STATIC CMOS RAM; File Size66KB，8 Pages; ManufacturerETC

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P4C1256-70L32M Overview

HIGH SPEED 32K x 8 STATIC CMOS RAM

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P4C1256

HIGH SPEED 32K x 8

STATIC CMOS RAM

FEATURES

High Speed (Equal Access and Cycle Times)

— 12/15/20/25/35 ns (Commercial)

— 15/20/25/35/45 ns (Industrial)

— 20/25/35/45/55/70 ns (Military)

Low Power

— 880 mW Active (Commercial)

Single 5V

10% Power Supply

Easy Memory Expansion Using

and

Inputs

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Fast t

Automatic Power Down

Packages

—28-Pin 300 mil DIP and SOJ

—28-Pin 600 mil Ceramic DIP

—28-Pin LCC(350 mil x 550 mil)

—32-Pin LCC (450 mil x 550 mil)

DESCRIPTION

The P4C1256 is a 262,144-bit high-speed CMOS

static RAM organized as 32Kx8. The CMOS memory

requires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V±10% tolerance power

supply.

Access times as fast as 12 nanoseconds permit greatly

enhanced system operating speeds. CMOS is utilized

to reduce power consumption to a low level. The

P4C1256 is a member of a family of PACE RAM™ prod-

ucts offering fast access times.

The P4C1256 device provides asynchronous operation with

matching access and cycle times. Memory locations are

specified on address pins A

to A

. Reading is accom-

plished by device selection (CE and output enabling (OE)

while write enable (WE) remains HIGH. By presenting the

address under these conditions, the data in the addressed

memory location is presented on the data input/output pins.

The input/output pins stay in the HIGH Z state when either

is HIGH or

is LOW.

Package options for the P4C1256 include 28-pin 300 mil

DIP and SOJ packages. For military temperature range,

Ceramic DIP and LCC packages are available.

FUNCTIONAL BLOCK DIAGRAM

ROW SELECT

•• •

PIN CONFIGURATIONS

VCC

(8)

262,144-BIT

MEMORY

ARRAY

A14

A13

A12

I/O1

32 31 30

A14

A 13

A 12

A 11

A 10

I/O8

I/O7

I/O

•••

••• •••

•••

I/0

COLUMN I/O

INPUT

DATA

CONTROL

• ••

•••

I/O

I/0

COLUMN

SELECT

14 15 16 17 18 19 20

I/O2

I/O3

GND

I/O4

I/O5

I/O6

I/0

GND

•••

(7)

DIP (P5, C5, D5-1), SOJ (J5)

TOP VIEW

1519B

32 LCC (L6)

TOP VIEW

See Selection Guide page for 28-pin LCC

Means Quality, Service and Speed

1Q97

117

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