P4C1256
HIGH SPEED 32K x 8
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
— 12/15/20/25/35 ns (Commercial)
— 15/20/25/35/45 ns (Industrial)
— 20/25/35/45/55/70 ns (Military)
Low Power
Single 5V±10% Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—28-Pin 300 mil DIP, SOJ, TSOP
—28-Pin 300 mil Ceramic DIP
—28-Pin 600 mil Ceramic DIP
—28-Pin CERPACK
—28-Pin SOP
—28-Pin LCC (350 mil x 550 mil)
—32-Pin LCC (450 mil x 550 mil)
DESCRIPTION
The P4C1256 is a 262,144-bit high-speed CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The
P4C1256 is a member of a family of PACE RAM™ prod-
ucts offering fast access times.
The P4C1256 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pins A
0
to A
14
. Reading
is accomplished by device selection (CE and output
enabling (OE) while write enable (WE) remains HIGH.
By presenting the address under these conditions, the
data in the addressed memory location is presented on
the data input/output pins. The input/output pins stay
in the HIGH Z state when either
CE
or
OE
is HIGH or
WE
is LOW.
Package options for the P4C1256 include 28-pin 300
mil DIP, SOJ and TSOP packages. For military tempera-
ture range, Ceramic DIP and LCC packages are avail-
able.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P5, C5, C5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)
CERPACK (F4) SIMILAR
1519B
See end of datasheet for LCC and TSOP
pin configurations.
Document #
SRAM119
REV G
1
Revised June 2007
P4C1256
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)
(5)
OE
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)
(5,7)
CE
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
transition LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM119
REV G
Page 5 of 17
Embedded System
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