P4C116/P4C116L
ULTRA HIGH SPEED 2K x 8
STATIC CMOS RAMS
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25/35 ns (Commercial)
– 15/20/25/35 ns (Military)
Low Power Operation
Output Enable Control Function
Single 5V±10% Power Supply
Common Data I/O
Fully TTL Compatible Inputs and Outputs
Produced with PACE II Technology
TM
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP, SOIC, SOJ
– 24-Pin Solder Seal Flat Pack
– 24-Pin Rectangular LCC (300 x 400 mils)
– 28-Pin Square LCC (450 x 450 mils)
– 32-Pin Rectangular LCC (450 x 550 mils)
– 40-Pin Square LCC (480 x 480 mils)
DESCRIPTION
The P4C116/P4C116L are 16,384-bit ultra high-speed
static RAMs organized as 2K x 8. The CMOS memories
require no clocks or refreshing and have equal access
and cycle times. Inputs are fully TTL-compatible. The
RAMs operate from a single 5V±10% tolerance power
supply. Current drain is typically 10 µA from a 2.0V
supply.
Access times as fast as 10 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOS is used to reduce power consumption.
The P4C116 is available in 24-pin 300 mil DIP, SOJ and
SOIC packages, a solder seal flatpack and 4 different
LCC packages (24, 28, 32, and 40 pin).
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P4, C4), SOJ (J4), SOIC (S4)
SOLDER SEAL FLAT PACK (FS-1) SIMILAR
LCC configurations at end of datasheet
Document #
SRAM110
REV A
1
Revised October 2005
P4C116/P4C116L
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
V
°C
RECOMMENDED OPERATING CONDITIONS
Grade
(2)
Commercial
Military
Ambient Temp
0°C to 70°C
-55°C to +125°C
Gnd
0V
0V
Vcc
5.0V ±10%
5.0V ±10%
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Conditions Typ. Unit
V
IN
= 0V
5
7
pF
pF
Output Capacitance V
OUT
= 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
CD
V
OL
V
OH
I
LI
I
LO
I
SB
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Input Clamp Diode Voltage V
CC
= Min., I
IN
= –18 mA
Output Low Voltage
I
OL
= +8 mA, V
CC
= Min.
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
Output Leakage Current
Standby Power Supply
Current (TTL Input Levels)
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.,
CE
= V
IH
,
V
OUT
= GND to V
CC
CE
≥
V
IH,
V
CC
= Max,
CE
≥
V
HC
,
V
CC
= Max,
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
f = Max., Outputs Open
Mil.
Ind./Com’l.
___
___
15
10
___
___
1
n/a
mA
Mil.
Com’l.
Mil.
Com’l.
Mil.
Ind./Com’l.
2.4
–10
–5
–10
–5
___
___
+10
+5
+10
+5
30
20
Test Conditions
P4C116
Min
Max
2.2
–0.5
(3)
–0.5
(3)
V
CC
+0.5
0.8
0.2
–1.2
0.4
2.4
–5
n/a
–5
n/a
___
___
+5
n/a
+5
n/a
20
n/a
P4C116L
Min
Max
2.2
–0.5
(3)
–0.5
(3)
V
CC
+0.5
0.8
0.2
–1.2
0.4
Unit
V
V
V
V
V
V
V
µA
µA
mA
V
CC
–0.2 V
CC
+0.5 V
CC
–0.2 V
CC
+0.5
I
SB1
Standby Power Supply
Current
(CMOS Input Levels)
n/a = Not Applicable
Document #
SRAM110
REV A
Page 2 of 14
P4C116/P4C116L
DATA RETENTION CHARACTERISTICS (P4C116L Military Temperature Only)
Symbol
V
DR
I
CCDR
t
CDR
t
R†
*T
A
= +25°C
§t
RC
= Read Cycle Time
†
Parameter
V
CC
for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery Time
Test Conditons
Min
2.0
Typ.*
V
CC
=
2.0V
3.0V
Max
V
CC
=
2.0V
3.0V
Unit
V
CE
≥
V
CC
–0.2V,
V
IN
≥
V
CC
–0.2V
or V
IN
≤
0.2V
0
t
RC§
10
15
600
900
µA
ns
ns
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
I
CC
Parameter
Dynamic Operating Current*
Temperature
Range
Commercial
Military
–10
180
N/A
–12
170
N/A
–15
160
170
–20
155
160
–25
150
155
–35
140
150
Unit
mA
mA
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
,
OE
= V
IH
.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Data Valid
–10
10
10
10
2
2
5
6
0
6
0
10
0
0
2
2
–12
12
12
12
2
2
6
8
0
7
0
12
–15
15
15
15
2
2
7
10
0
8
0
15
–20
20
20
20
2
3
8
10
0
9
0
20
–25
25
25
25
2
3
10
15
0
12
0
20
–35
35
35
35
Min Max Min Max Min Max Min Max Min Max Min Max
Unit
ns
ns
ns
ns
ns
15
20
15
25
ns
ns
ns
ns
ns
ns
t
OLZ
Output Enable Low to Low Z
t
OHZ
Output Enable High to High Z
t
PU
t
PD
Chip Enable to Power Up Time
Chip Disable to Power Down
Document #
SRAM110
REV A
Page 3 of 14
P4C116/P4C116L
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)
(5)
OE
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)
(5,7)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM110
REV A
Page 4 of 14
P4C116/P4C116L
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V ± 10%, All Temperature Ranges)
(2)
Sym.
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
–10
10
8
8
0
8
0
7
0
6
0
0
–12
12
10
10
0
10
0
8
0
7
0
–15
15
12
12
0
12
0
10
0
8
0
–20
–25
25
18
18
0
18
0
15
0
–35
35
25
25
0
20
0
20
0
Min Max Min Max Min Max Min Max Min Max Min Max
20
15
15
0
15
0
12
0
10
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
15
0
15
ns
ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(10,11)
WE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)
(10)
CE
Notes:
10.
CE
and
WE
must be LOW for WRITE cycle.
11.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
12. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM110
REV A
Page 5 of 14
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