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P4C1049-25JMB

Description
HIGH SPEED 512K x 8 STATIC CMOS RAM
Categorystorage    storage   
File Size211KB,12 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C1049-25JMB Overview

HIGH SPEED 512K x 8 STATIC CMOS RAM

P4C1049-25JMB Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPyramid Semiconductor Corporation
Parts packaging codeSOJ
package instructionSOJ,
Contacts36
Reach Compliance Codecompliant
ECCN code3A001.A.2.C
Maximum access time25 ns
JESD-30 codeR-PDSO-J36
JESD-609 codee0
length23.495 mm
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals36
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize512KX8
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Filter levelMIL-STD-883 Class B
Maximum seat height3.683 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
P4C1049/P4C1049L
HIGH SPEED 512K x 8
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
— 15/20/25 ns (Commercial)
— 20/25/35 ns (Industrial)
— 20/25/35/45/55/70 ns (Military)
Low Power
Single 5V±10% Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—36-Pin SOJ (400 mil)
—36-Pin FLATPACK
—36-Pin LCC (452 mil x 920 mil)
DESCRIPTION
The P4C1049 is a 4 Megabit high-speed CMOS
static RAM organized as 512Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times as fast as 15 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The P4C1049
is a member of a family of PACE RAM™ products offer-
ing fast access times.
The P4C1049 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pins A
0
to A
18
. Reading is
accomplished by device selection (CE) and output en-
abling (OE) while write enable (WE) remains HIGH. By
presenting the address under these conditions, the data
in the addressed memory location is presented on the
data input/output pins. The input/output pins stay in the
HIGH Z state when either
CE
or
OE
is HIGH or
WE
is
LOW.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
SOLDER-SEAL
FLATPACK (FS-4)
SOJ (J9)
LCC (L11)
1519B
Document #
SRAM128
REV OR
1
Revised October 2005
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