P4C1049-20FS36C datasheet, PDF

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P4C1049-20FS36C: DescriptionHIGH SPEED 512K x 8 STATIC CMOS RAM; Categorystorage storage; File Size211KB，12 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P4C1049-20FS36C Overview

HIGH SPEED 512K x 8 STATIC CMOS RAM

P4C1049-20FS36C Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	Pyramid Semiconductor Corporation
Parts packaging code	DFP
package instruction	DFP,
Contacts	36
Reach Compliance Code	compli
ECCN code	3A991.B.2.A
Maximum access time	20 ns
JESD-30 code	R-PDFP-F36
length	23.368 mm
memory density	4194304 bi
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	36
word count	524288 words
character code	512000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX8
Package body material	PLASTIC/EPOXY
encapsulated code	DFP
Package shape	RECTANGULAR
Package form	FLATPACK
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	3.175 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	FLAT
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	12.954 mm

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P4C1049/P4C1049L

HIGH SPEED 512K x 8

STATIC CMOS RAM

FEATURES

High Speed (Equal Access and Cycle Times)

— 15/20/25 ns (Commercial)

— 20/25/35 ns (Industrial)

— 20/25/35/45/55/70 ns (Military)

Low Power

Single 5V±10% Power Supply

Easy Memory Expansion Using

and

Inputs

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Automatic Power Down

Packages

—36-Pin SOJ (400 mil)

—36-Pin FLATPACK

—36-Pin LCC (452 mil x 920 mil)

DESCRIPTION

The P4C1049 is a 4 Megabit high-speed CMOS

static RAM organized as 512Kx8. The CMOS memory

requires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V±10% tolerance power

supply.

Access times as fast as 15 nanoseconds permit greatly

enhanced system operating speeds. CMOS is utilized

to reduce power consumption to a low level. The P4C1049

is a member of a family of PACE RAM™ products offer-

ing fast access times.

The P4C1049 device provides asynchronous operation

with matching access and cycle times. Memory loca-

tions are specified on address pins A

to A

. Reading is

accomplished by device selection (CE) and output en-

abling (OE) while write enable (WE) remains HIGH. By

presenting the address under these conditions, the data

in the addressed memory location is presented on the

data input/output pins. The input/output pins stay in the

HIGH Z state when either

is HIGH or

LOW.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATIONS

SOLDER-SEAL

FLATPACK (FS-4)

SOJ (J9)

LCC (L11)

1519B

Document #

SRAM128

REV OR

Revised October 2005

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