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P4C1048L-55TI

Description
LOW POWER 512K x 8 CMOS STATIC RAM
Categorystorage    storage   
File Size157KB,12 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C1048L-55TI Overview

LOW POWER 512K x 8 CMOS STATIC RAM

P4C1048L-55TI Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPyramid Semiconductor Corporation
Parts packaging codeTSOP2
package instructionTSOP2,
Contacts32
Reach Compliance Codecompliant
ECCN code3A991.B.2.A
Maximum access time55 ns
JESD-30 codeR-PDSO-G32
length20.96 mm
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize512KX8
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP2
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.04 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width10.16 mm
Base Number Matches1
P4C1048L
LOW POWER 512K x 8
CMOS STATIC RAM
FEATURES
V
CC
Current
— Operating: 35mA
— CMOS Standby: 100µA
Access Times
—45/55/70/100 ns
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 600 mil Plastic and Ceramic DIP
—32-Pin 445 mil SOP
—32-Pin TSOP II
DESCRIPTION
The P4C1048L is a 4 Megabit low power CMOS static
RAM organized as 512K x 8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times as fast as 45 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1048L device provides asynchronous opera-
tion with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
18
. Read-
ing is accomplished by device selection (CE low) and
output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these condi-
tions, the data in the addressed memory location is pre-
sented on the data input/output pins. The input/output
pins stay in the HIGH Z state when either
CE
is HIGH or
WE
is LOW.
The P4C1048L is packaged in a 32-pin 445 mil plastic
SOP, 32-pin TSOP II, or 600 mil plastic or ceramic side-
brazed DIP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P600, C10),
SOP (S12), TSOP II (T4)
TOP VIEW
Document #
SRAM129
REV D
Revised July 2007
1
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