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P4C1026-25J4M

Description
ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM
Categorystorage    storage   
File Size286KB,10 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C1026-25J4M Overview

ULTRA HIGH SPEED 256K x 4 STATIC CMOS RAM

P4C1026-25J4M Parametric

Parameter NameAttribute value
package instructionSOJ,
Reach Compliance Codecompli
Maximum access time25 ns
JESD-30 codeR-PDSO-J28
length18.415 mm
memory density1048576 bi
Memory IC TypeSTANDARD SRAM
memory width4
Number of functions1
Number of terminals28
word count262144 words
character code256000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize256KX4
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Maximum seat height3.7592 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
width10.16 mm
Base Number Matches1
P4C1026
ULTRA HIGH SPEED 256K x 4
STATIC CMOS RAM
FEATURES
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
– 15/20/25/35 ns (Commercial/Industrial)
– 20/25/35 ns (Military)
Low Power
Single 5V±10% Power Supply
Data Retention with 2.0V Supply
Three-State Outputs
TTL/CMOS Compatible Outputs
Fully TTL Compatible Inputs
Standard Pinout (JEDEC Approved)
– 28-Pin 300 mil SOJ
– 28-Pin 400 mil SOJ
– 28-Pin 400 mil Ceramic DIP
– 32-Pin Ceramic LCC
DESCRIPTION
The P4C1026 is a 1 Meg ultra high speed static RAM
organized as 256K x 4. The CMOS memory requires no clock
or refreshing and has equal access and cycle times. Inputs
and outputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply. With battery
backup, data integrity is maintained for supply voltages down
to 2.0V.
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption.
The P4C1026 is available in a 28-pin 300 mil and 400 mil SOJ
packages, as well as Ceramic DIP and LCC packages,
providing excellent board level densities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
SOJ (J5, J7), DIP (C7)
LCC(L13)
Document #
SRAM127
REV E
1
Revised April 2007
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