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P4C1024L70SC

Description
LOW POWER 128K x 8 CMOS STATIC RAM
Categorystorage    storage   
File Size278KB,11 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C1024L70SC Overview

LOW POWER 128K x 8 CMOS STATIC RAM

P4C1024L70SC Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeSOIC
package instructionSOP, SOP32,.56
Contacts32
Reach Compliance Codecompli
ECCN codeEAR99
Maximum access time70 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-G32
JESD-609 codee0
length20.447 mm
memory density1048576 bi
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP32,.56
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height2.9972 mm
Maximum standby current0.00003 A
Minimum standby current2 V
Maximum slew rate0.07 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width11.303 mm
Base Number Matches1
P4C1024L
LOW POWER 128K x 8
CMOS STATIC RAM
FEATURES
V
CC
Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CE
1,
CE
2
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 600 mil Plastic and Ceramic DIP
—32-Pin 445 mil SOP
—32-Pin TSOP
DESCRIPTION
The P4C1024L is a 1,048,576-bit low power CMOS static
RAM organized as 128Kx8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1024L device provides asynchronous opera-
tion with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
. Read-
ing is accomplished by device selection (CE
1
low and
CE
2
high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory lo-
cation is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
The P4C1024L is packaged in a 32-pin TSOP, 445 mil
SOP, and a 600 mil PDIP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P600, C10), SOP (S12)
TOP VIEW
See end of datasheet for TSOP pin configuration.
Document #
SRAM125
REV C
Revised September 2006
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