P4C1024L70TC datasheet, PDF - EEWORLD Datasheet

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P4C1024L70TC: DescriptionLOW POWER 128K x 8 CMOS STATIC RAM; Categorystorage storage; File Size278KB，11 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P4C1024L70TC Overview

LOW POWER 128K x 8 CMOS STATIC RAM

P4C1024L70TC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	TSOP
package instruction	8 X 20 MM, TSOP-32
Contacts	32
Reach Compliance Code	unknow
Maximum access time	70 ns
JESD-30 code	R-PDSO-G32
length	18.4 mm
memory density	1048576 bi
Memory IC Type	STANDARD SRAM
memory width	8
Number of functions	1
Number of terminals	32
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128KX8
Package body material	PLASTIC/EPOXY
encapsulated code	LSSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	1.2192 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8 mm
Base Number Matches	1

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P4C1024L

LOW POWER 128K x 8

CMOS STATIC RAM

FEATURES

Current (Commercial/Industrial)

— Operating: 70mA/85mA

— CMOS Standby: 100µA/100µA

Access Times

—55/70 (Commercial or Industrial)

Single 5 Volts ±10% Power Supply

Easy Memory Expansion Using

and

Inputs

Common Data I/O

Three-State Outputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Automatic Power Down

Packages

—32-Pin 600 mil Plastic and Ceramic DIP

—32-Pin 445 mil SOP

—32-Pin TSOP

DESCRIPTION

The P4C1024L is a 1,048,576-bit low power CMOS static

RAM organized as 128Kx8. The CMOS memory re-

quires no clocks or refreshing, and has equal access

and cycle times. Inputs are fully TTL-compatible. The

RAM operates from a single 5V±10% tolerance power

supply.

Access times of 55 ns and 70 ns are availale. CMOS is

utilized to reduce power consumption to a low level.

The P4C1024L device provides asynchronous opera-

tion with matching access and cycle times. Memory

locations are specified on address pins A

to A

. Read-

ing is accomplished by device selection (CE

low and

high) and output enabling (OE) while write enable

(WE) remains HIGH. By presenting the address under

these conditions, the data in the addressed memory lo-

cation is presented on the data input/output pins. The

input/output pins stay in the HIGH Z state when either

is HIGH or

or CE

is LOW.

The P4C1024L is packaged in a 32-pin TSOP, 445 mil

SOP, and a 600 mil PDIP.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

DIP (P600, C10), SOP (S12)

TOP VIEW

See end of datasheet for TSOP pin configuration.

Document #

SRAM125

REV C

Revised September 2006

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