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P4C1024-17P3C

Description
HIGH SPEED 128K X 8 CMOS STATIC RAM
Categorystorage    storage   
File Size87KB,8 Pages
ManufacturerPyramid Semiconductor Corporation
Websitehttp://www.pyramidsemiconductor.com/
Download Datasheet Parametric View All

P4C1024-17P3C Overview

HIGH SPEED 128K X 8 CMOS STATIC RAM

P4C1024-17P3C Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPyramid Semiconductor Corporation
Parts packaging codeDIP
package instructionDIP, DIP32,.3
Contacts32
Reach Compliance Codecompli
ECCN code3A991.B.2.B
Maximum access time17 ns
I/O typeCOMMON
JESD-30 codeR-PDIP-T32
JESD-609 codee0
length40.64 mm
memory density1048576 bi
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize128KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP32,.3
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum standby current0.02 A
Minimum standby current4.5 V
Maximum slew rate0.18 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
P4C1024
P4C1024
HIGH SPEED 128K x 8
CMOS STATIC RAM
FEATURES
High Speed (Equal Access and Cycle Times)
— 15/17/20/25/35 ns (Commercial)
— 20/25/35/45 ns (Industrial)
Single 5 Volts
±
10% Power Supply
Easy Memory Expansion Using
CE
1,
CE
2
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—32-Pin 300 mil DIP and SOJ
—32-Pin 400 mil SOJ
DESCRIPTION
The P4C1024 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
The P4C1024 device provides asynchronous opera-
tions with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
. Read-
ing is accomplished by device selection (CE
1
low and
CE
2
high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory
Access times of 15 nanoseconds permit greatly en- location is presented on the data input/output pins. The
hanced system operating speeds. CMOS is utilized to input/output pins stay in the HIGH Z state when either
reduce power consumption to a low level. The P4C1024
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
is a member of a family of PACE RAM™ products offer-
ing fast access times.
Package options for the P4C1024 include 32-pin 300
mil DIP and SOJ packages as well as 400 mil SOJ.
FUNCTIONAL BLOCK DIAGRAM
ROW SELECT
A
•••
PIN CONFIGURATION
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
1024.2
(9)
A
262,144-
BIT
MEMORY
ARRAY
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
I/O
1
••• •••
••• •••
••• •••
INPUT
DATA
CONTROL
COLUMN
I/O
I/O
2
COLUMN
SELECT
WE
CE1
CE2
OE
CONTROL
CIRCUIT
A
•••
•••
GND
A
1024.1
(8)
DIP (P300), SOJ (J300, J400)
TOP VIEW
Means Quality, Service and Speed
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