P4C1023/P4C1023L
LOW POWER 128K x 8
SINGLE CHIP ENABLE
CMOS STATIC RAM
FEATURES
V
CC
Current
— Operating: 35mA
— CMOS Standby: 100µA
Access Times
—55/70 ns
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 400 or 600 mil Ceramic DIP
—32-Pin Ceramic SOJ
DESCRIPTION
The P4C1023L is a 1 Megabit low power CMOS static
RAM organized as 128K x 8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1023L device provides asynchronous opera-
tion with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
. Read-
ing is accomplished by device selection (CE low) and
output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these condi-
tions, the data in the addressed memory location is pre-
sented on the data input/output pins. The input/output
pins stay in the HIGH Z state when either
CE
is HIGH or
WE
is LOW.
The P4C1023L is packaged in a 32-pin 400 or 600 mil
ceramic DIP and in a 32-pin ceramic SOJ.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (C10, C11), CERAMIC SOJ (CJ1)
TOP VIEW
Document #
SRAM126
REV OR
Revised October 2005
1
P4C1023/P4C1023L
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Commercial (0°C to 70°C)
Industrial (-40°C to 85°C)
Military (-55°C to 125°C)
Supply Voltage
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
4.5V
≤
V
CC
≤
5.5V
MAXIMUM RATINGS
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only.
Functional operation of the device is not implied at these or any other conditions in excess of those given in the opera-
tional sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device
reliability.
Symbol
V
CC
V
TERM
T
A
S
TG
I
OUT
I
LAT
Parameter
Supply Voltage with Respect to GND
Terminal Voltage with Respect to GND (up to 7.0V)
Operating Ambient Temperature
Storage Temperature
Output Current into Low Outputs
Latch-up Current
>200
Min
-0.5
-0.5
-55
-65
Max
7.0
V
CC
+ 0.5
125
150
25
Unit
V
V
°C
°C
mA
mA
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
Parameter
Output High Voltage
(I/O
0
- I/O
7
)
Output Low Voltage
(I/O
0
- I/O
7
)
Input High Voltage
Input Low Voltage
Input Leakage Current
GND
≤
V
IN
≤
V
CC
Comm.
Industrial
Military
Comm.
Industrial
Military
I
SB
V
CC
Current
TTL Standby Current
(TTL Input Levels)
V
CC
Current
CMOS Standby Current
(CMOS Input Levels)
V
CC
= 5.5V, I
OUT
= 0 mA
CE
1
= V
IH
or CE
2
= V
IL
V
CC
= 5.5V, I
OUT
= 0 mA
CE
1
≥
V
CC
-0.2V, CE
2
≤
0.2V
100
µA
Test Conditions
I
OH
= –1mA, V
CC
= 4.5V
I
OL
= 2.1mA
2.2
-0.3
-2
-5
-10
-2
-5
-10
Min
2.4
0.4
V
CC
+ 0.3
0.8
+2
+5
+10
+2
+5
+10
3
mA
Max
Unit
V
V
V
V
µA
GND
≤
V
OUT
≤
V
CC
I
LO
Output Leakage Current
CE
1
≥
V
IH
or CE
2
≤
V
IL
µA
I
SB1
Document #
SRAM126
REV OR
Page 2 of 11
P4C1023/P4C1023L
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Max
7
9
Unit
pF
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature
Range
Commercial
I
CC
Dynamic Operating Current
Industrial
Military
Note 1
-55
-70
20
25
35
20
25
35
mA
Unit
Note 1 -
Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e., CE
2
≥
V
IH
(min),
CE
1
and
WE
≤
V
IL
(max),
OE
is high. Switching
inputs are 0V and 3V.
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable Low
to Data Valid
Output Enable Low to
Low Z
Output Enable High
to High Z
Chip Enable to Power
Up Time
Chip Disable to
Power Down Time
0
55
5
20
0
70
-55
Min
55
55
55
5
10
20
30
5
25
5
10
25
35
Max
Min
70
70
70
-70
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #
SRAM126
REV OR
Page 3 of 11
P4C1023/P4C1023L
READ CYCLE NO. 1 (OE CONTROLLED)
(1)
OE
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
CE
READ CYCLE NO. 3 (CE CONTROLLED)
Notes:
1.
WE
is HIGH for READ cycle.
2.
CE
and
OE
are LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE
transition LOW.
4. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter
is sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the
first transitioning address.
Document #
SRAM126
REV OR
Page 4 of 11
P4C1023/P4C1023L
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time
to End of Write
Address Valid to
End of Write
Address Set-up Time
Write Pulse Width
Address Hold Time
Data Valid to End
of Write
Data Hold Time
Write Enable to
Output in High Z
Output Active from
End of Write
5
-55
Min
55
50
50
0
40
0
25
0
25
5
Max
Min
70
60
60
0
50
0
30
0
30
-70
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE NO. 1 (WE CONTROLLED)
(6)
WE
Notes:
6.
CE
and
WE
are LOW for WRITE cycle.
7.
OE
is LOW for this WRITE cycle to show twz and tow.
8. Write Cycle Time is measured from the last valid address to the first transitioning address.
Document #
SRAM126
REV OR
Page 5 of 11
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