P3C1256
HIGH SPEED 32K x 8
3.3V STATIC CMOS RAM
FEATURES
3.3V Power Supply
High Speed (Equal Access and Cycle Times)
— 12/15/20/25 ns (Commercial)
— 15/20/25 ns (Industrial)
Low Power
Single 3.3 Volts ±0.3Volts Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin TSOP and SOJ
DESCRIPTION
The P3C1256 is a 262,144-bit high-speed CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 3.3V± 0.3V tolerance power
supply.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The
P3C1256 is a member of a family of PACE RAM™ prod-
ucts offering fast access times.
The P3C1256 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pins A
0
to A
14
. Reading is
accomplished by device selection (CE and output en-
abling (OE) while write enable (WE) remains HIGH. By
presenting the address under these conditions, the data
in the addressed memory location is presented on the
data input/output pins. The input/output pins stay in the
HIGH Z state when either
CE
or
OE
is HIGH or
WE
is
LOW.
Package options for the P3C1256 include 28-pin TSOP
and SOJ packages.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
SOJ (J5)
1519B
TOP VIEW
See end of datasheet for TSOP pin configuration
Document #
SRAM122
REV B
1
Revised August 2006
P3C1256
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient)
Commercial (0°C to 70°C)
Industrial (-40°C to 85°C)
Supply Voltage
3.0V
≤
V
CC
≤
3.6V
3.0
≤
V
CC
≤
3.6V
MAXIMUM RATINGS
(1)
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings
only. Functional operation of the device is not implied at these or any other conditions in excess of those given in
the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely
affect device reliability.
Symbol
V
CC
V
TERM
T
A
S
TG
I
OUT
I
LAT
Parameter
Supply Voltage with Respect to GND
Terminal Voltage with Respect to GND (up to 7.0V)
Operating Ambient Temperature
Storage Temperature
Output Current into Low Outputs
Latch-up Current
>200
Min
-0.5
-0.5
-40
-55
Max
7.0
V
CC
+ 0.5
85
125
25
Unit
V
V
°C
°C
mA
mA
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Symbol
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
I
SB
I
SB1
Parameter
Output High Voltage
(I/O
0
- I/O
7
)
Output Low Voltage
(I/O
0
- I/O
8
)
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
V
CC
Current
TTL Standby Current
V
CC
Current
CMOS Standby Current
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
CE
= V
CC
V
CC
= 3.6V, I
OUT
= 0 mA
CE
= V
CC
V
CC
= 3.6V, I
OUT
= 0 mA
CE
= V
CC
Test Conditions
I
OH
= –4mA, V
CC
= 3.0V
I
OL
= 8 mA
I
OL
= 10 mA
2.2
-0.5
(3)
-5
-5
Min
2.4
0.4
0.5
V
CC
+ 0.3
0.8
+5
+5
20
Max
Unit
V
V
V
V
V
µA
µA
mA
3
mA
Document #
SRAM122
REV B
Page 2 of 10
P3C1256
CAPACITANCES
(4)
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Max
10
10
Unit
pF
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
I
CC
Parameter
Dynamic Operating Current
Temperature
Test
Range
Conditions
Commercial
Industrial
*
*
-12
110
N/A
-15
100
115
-20
95
110
-25
90
105
Unit
mA
mA
*Tested
with outputs open and all address and data inputs changing at the maximum write-cycle rate.
The device is continuously enabled for writing, i.e.,
CE,
and
WE
≤
V
IL
(max),
OE
is high. Switching inputs are 0V
and 3V.
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access
Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable Low
to Data Valid
Output Enable Low to
Low Z
Output Enable High
to High Z
Chip Enable to Power
Up Time
Chip Disable to
Power Down Time
0
12
0
6
0
15
-12
Min
12
12
12
2
2
7
7
0
7
0
20
2
2
8
9
0
9
0
20
Max
Min
15
15
15
2
2
9
11
0
10
-15
Max
Min
20
20
20
2
2
10
12
-20
Max
Min
25
25
25
-25
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #
SRAM122
REV B
Page 3 of 10
P3C1256
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)
(5)
OE
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE CONTROLLED)
(5,7)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
transition
LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM122
REV B
Page 4 of 10
P3C1256
AC CHARACTERISTICS—WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time to
End of Write
Address Valid to
End of Write
Address Set-up
Time
Write Pulse Width
Address Hold Time
Data Valid to End of
Write
Data Hold Time
Write Enable to
Output in High Z
Output Active from
End of Write
3
-12
Min
12
10
10
0
9
0
8
0
7
3
Max
Min
15
12
12
0
11
0
10
0
8
3
-15
Max
Min
20
15
15
0
15
0
12
0
10
3
-20
Max
Min
25
18
18
0
18
0
15
0
11
-25
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(10,11)
Notes:
10.
CE
and
WE
must be LOW for WRITE cycle.
11.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
12. If
CE
goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM122
REV B
Page 5 of 10
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