P3C1011-35JM datasheet, PDF - EEWORLD Datasheet

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P3C1011-35JM: DescriptionHIGH SPEED 128K x 16 (2 MEG) STATIC CMOS RAM; Categorystorage storage; File Size110KB，10 Pages; ManufacturerPyramid Semiconductor Corporation; Websitehttp://www.pyramidsemiconductor.com/

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P3C1011-35JM Overview

HIGH SPEED 128K x 16 (2 MEG) STATIC CMOS RAM

P3C1011-35JM Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	SOJ
package instruction	SOJ,
Contacts	44
Reach Compliance Code	compli
ECCN code	3A001.A.2.C
Maximum access time	35 ns
JESD-30 code	R-PDSO-J44
JESD-609 code	e0
length	28.575 mm
memory density	2097152 bi
Memory IC Type	STANDARD SRAM
memory width	16
Number of functions	1
Number of terminals	44
word count	131072 words
character code	128000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	128KX16
Package body material	PLASTIC/EPOXY
encapsulated code	SOJ
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	3.759 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	TIN LEAD
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	10.16 mm
Base Number Matches	1

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P3C1011

HIGH SPEED 128K x 16 (2 MEG)

STATIC CMOS RAM

FEATURES

High Speed (Equal Access and Cycle Times)

— 10/12/15/20 ns (Commercial)

— 12/15/20 ns (Industrial)

— 20/25/35 (Military)

Low Power

— 360 mW (max.)

Single 3.3V ± 0.3V Power Supply

2.0V Data Retention

Easy Memory Expansion Using

and

Inputs

Fully TTL Compatible Inputs and Outputs

Advanced CMOS Technology

Fast t

Automatic Power Down when deselected

Packages

—44-Pin SOJ, TSOP II

DESCRIPTION

The P3C1011 is a 131,072 words by 16 bits high-speed

CMOS static RAM. The CMOS memory requires no

clocks or refreshing, and has equal access and cycle

times. Inputs are fully TTL-compatible. The RAM oper-

ates from a single 3.3V ± 0.3V tolerance power

supply.

Access times as fast as 10 nanoseconds permit greatly

enhanced system operating speeds. CMOS is utilized

to reduce power consumption to a low level. The P3C1011

is a member of a family of PACE RAM™ products offer-

ing fast access times.

The P3C1011 device provides asynchronous operation

with matching access and cycle times. Memory loca-

tions are specified on address pins A

to A

. Reading is

accomplished by device selection (CE and output en-

abling (OE) while write enable (WE) remains HIGH. By

presenting the address under these conditions, the data

in the addressed memory location is presented on the

data input/output pins. The input/output pins stay in the

HIGH Z state when either

is HIGH or

LOW.

For both reading and writing, the Byte Enable control lines

(BLE for I/O

0-7

and

BHE

for I/O

8-15

) allow for the selection

of only 8 of the 16 I/O lines if desired. When a Byte

Enable control line is HIGH, the corresponding I/Os are

active.

Package options for the P3C1011 include 44-pin SOJ and

TSOP packages.

FUNCTIONAL BLOCK DIAGRAM

PIN CONFIGURATION

1519B

SOJ

TSOP II

Document #

SRAM131

REV OR

Revised March 2006

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