P3C1011
HIGH SPEED 128K x 16 (2 MEG)
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
— 10/12/15/20 ns (Commercial)
— 12/15/20 ns (Industrial)
— 20/25/35 (Military)
Low Power
— 360 mW (max.)
Single 3.3V ± 0.3V Power Supply
2.0V Data Retention
Easy Memory Expansion Using
CE
and
OE
Inputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down when deselected
Packages
—44-Pin SOJ, TSOP II
DESCRIPTION
The P3C1011 is a 131,072 words by 16 bits high-speed
CMOS static RAM. The CMOS memory requires no
clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM oper-
ates from a single 3.3V ± 0.3V tolerance power
supply.
Access times as fast as 10 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The P3C1011
is a member of a family of PACE RAM™ products offer-
ing fast access times.
The P3C1011 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pins A
0
to A
17
. Reading is
accomplished by device selection (CE and output en-
abling (OE) while write enable (WE) remains HIGH. By
presenting the address under these conditions, the data
in the addressed memory location is presented on the
data input/output pins. The input/output pins stay in the
HIGH Z state when either
CE
or
OE
is HIGH or
WE
is
LOW.
For both reading and writing, the Byte Enable control lines
(BLE for I/O
0-7
and
BHE
for I/O
8-15
) allow for the selection
of only 8 of the 16 I/O lines if desired. When a Byte
Enable control line is HIGH, the corresponding I/Os are
active.
Package options for the P3C1011 include 44-pin SOJ and
TSOP packages.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
1519B
SOJ
TSOP II
Document #
SRAM131
REV OR
Revised March 2006
1
P3C1011
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
Operating Temperature
Value
–0.5 to +4.6
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
V
°C
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
DC Output Current
Value
–55 to +125
–65 to +150
20
Unit
°C
°C
mA
V
TERM
T
A
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
(2)
Industrial
Commercial
Military
Ambient
Temperature
–40°C to +85°C
0°C to +70°C
-55°C to +125°C
V
SS
0V
0V
0V
V
CC
3.3V ± 0.3V
3.3V ± 0.3V
3.3V ± 0.3V
CAPACITANCES
(4)
V
CC
= 3.3V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
I/O Capacitance
Conditions Typ. Unit
V
IN
= 0V
V
OUT
= 0V
8
8
pF
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
OL
V
OH
Parameter
Input High Voltage
Input Low Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
I
OL
= +8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
V
CC
= Max.,
I
LO
Output Leakage Current
CE
= V
IH
,
V
OUT
= GND to V
CC
CE
≥
V
IH
I
SB
Standby Power Supply
V
CC
= Max,
Current (TTL Input Levels) f = Max., Outputs Open
V
IN
≥
V
IH
or V
IN
≤
V
IL
CE
≥
V
CC
- 0.2V
I
SB1
Standby Power Supply
Current
(CMOS Input Levels)
V
CC
= Max,
f = 0, Outputs Open
V
IN
≥
V
CC
- 0.3V or
V
IN
≤
0.3V
___
10
mA
___
40
mA
-1
+1
µA
2.4
-1
+1
Test Conditions
P3C1011
Unit
Min
Max
V
CC
+0.3 V
2.0
–0.3
(3)
0.8
0.4
V
V
V
µA
I
LI
Document #
SRAM131
REV OR
Page 2 of 10
P3C1011
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature
Range
Commercial
–10
90
N/A
N/A
–12
85
95
N/A
–15
80
90
N/A
–20
75
85
100
–25
70
80
95
–35
65
75
90
Unit
mA
mA
mA
I
CC
Dynamic Operating Current* Industrial
Military
*V
CC
= 3.6V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
,
OE
= V
IH
.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 3.3V ± 0.3V, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Data Valid
3
3
-10
10
10
10
3
3
5
5
12
-12
15
12
12
3
3
6
6
-15
20
15
15
3
3
7
7
-20
-25
-35
Unit
ns
35
35
ns
ns
ns
ns
12
12
ns
ns
Min Max Min Max Min Max Min Max Min Max Min Max
25
20
20
3
3
8
8
10
10
25
25
35
3
3
t
OLZ
t
OHZ
t
PU
t
PD
t
BE
t
LZBE
t
HZBE
Output Enable Low to Low Z
Output Enable High to High Z
Chip Enable to Power Up Time
Chip Disable to Power Down Time
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
0
5
0
10
5
0
6
0
6
0
12
6
0
6
0
7
0
15
7
0
7
0
8
0
20
8
0
8
0
10
0
25
10
0
10
0
12
0
35
12
0
12
ns
ns
ns
ns
ns
ns
ns
Document #
SRAM131
REV OR
Page 3 of 10
P3C1011
TIMING WAVEFORM OF READ CYCLE NO. 1
TIMING WAVEFORM OF READ CYCLE NO. 2 (OE CONTROLLED)
(5,6)
OE
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
not more negative than –2.0V and
V
IH
≤
V
CC
+ 0.5V, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
transition LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM131
REV OR
Page 4 of 10
P3C1011
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 3.3V ± 0.3V, All Temperature Ranges)
(2)
Sym.
t
WC
t
CW
Parameter
Write Cycle Time
Chip Enable Time to End of
Write
Address Valid to End of Write
Address Set-up Time to Write
Start
Write Pulse Width
Address Hold Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
WE
High to Low Z
Byte Enable to End of Write
-10
10
7
12
8
-12
15
10
-15
20
10
-20
25
12
-25
35
15
-35
Min Max Min Max Min Max Min Max Min Max Min Max
Unit
ns
ns
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
t
LZWE
t
BW
7
0
7
0
5
0
5
3
3
7
8
0
8
0
6
0
6
3
3
8
10
0
10
0
7
0
7
3
3
10
10
0
10
0
8
0
8
3
3
10
12
0
12
0
10
0
10
3
3
12
15
0
15
0
12
0
12
3
3
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (CE CONTROLLED)
CE
Document #
SRAM131
REV OR
Page 5 of 10
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