AS4SD8M16DGC-75/IT datasheet, PDF

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AS4SD8M16DGC-75/IT: DescriptionSynchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54; Categorystorage storage; File Size4MB，55 Pages; ManufacturerMicross; Websitehttps://www.micross.com

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AS4SD8M16DGC-75/IT Overview

Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54

AS4SD8M16DGC-75/IT Parametric

Parameter Name	Attribute value
Maker	Micross
Parts packaging code	TSOP2
package instruction	TSOP2,
Contacts	54
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	5.4 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G54
JESD-609 code	e0
length	22.22 mm
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	TIN LEAD
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	DUAL
width	10.16 mm

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AS4SD8M16

128 Mb: 8 Meg x 16 SDRAM

Synchronous DRAM Memory

FEATURES

•

Full Military temp (-55°C to 125°C) processing available

Copper lead frame option for enhanced reliability

Conﬁguration: 8 Meg x 16 (2 Meg x 16 x 4 banks)

Fully synchronous; all signals registered on positive

edge of system clock

Internal pipelined operation; column address can be

changed every clock cycle

Internal banks for hiding row access/precharge

Programmable burst lengths: 1, 2, 4, 8 or full page

Auto Precharge, includes CONCURRENT AUTO

PRECHARGE and Auto Refresh Modes

Self Refresh Mode (IT & ET)

64ms, 4,096-cycle refresh (IT)

24ms 4,096 cycle recfresh (XT)

WRITE Recovery (t

= “2 CLK”)

LVTTL-compatible inputs and outputs

Single +3.3V ±0.3V power supply

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQML

WE\

CAS\

RAS\

CS\

BA0

BA1

A10

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

DQMH

CLK

CKE

A11

Vss

SDRAM

PIN ASSIGNMENT

(Top View)

54-Pin TSOP

OPTIONS

•

MARKING

Plastic Package –54-pin TSOPII (400 mil)

- Alloy 42 lead frame - OCPL*

DG No. 901

- Copper lead frame

DGC

(Pb/Sn

ﬁ

nish or RoHS available)

•

Timing (Cycle Time)

7.5ns @ CL = 3 (PC133) or

7.5ns @ CL = 2 (PC100)

Operating Temperature Ranges

-Industrial Temp (-40°C to 85° C)

-Enhanced Temp

(-40°C to +105°C)

-Military Temp (-55°C to 125°C)

-75

•

8 Meg x 16

Configuration

2 Meg x 16 x 4 banks

Refresh Count

Row Addressing

4K (A0-A11)

Bank Addressing

4 (BA0, BA1)

Column Addressing

512 (A0-A8)

Note: “\” indicates an active low.

KEY TIMING PARAMETERS

SPEED

CLOCK

ACCESS TIME

GRADE FREQUENCY CL = 2** CL = 3**

-75

133 MHz

–

5.4ns

-75

100 MHz

6ns

–

*Off-center parting line

**CL = CAS (READ) latency

SETUP

TIME

1.5ns

HOLD

TIME

0.8ns

For more products and information

please visit our web site at

www.micross.com

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4SD8M16

Rev. 1.1 04/10

AS4SD8M16

ENHANCING RELIABILITY WITH COPPER LEAD FRAMES

ADVANTAGES & BENEFITS

Superior thermal conductivity improvement: 170 W/m*K

vs. 14 W/m*K (a 12X difference).

•

ja and

jc characteristics provide up to 3.8X advantage

of heat dissipation capability versus parts with alloy 42

lead frames.

• Heat dissipated from the die faster makes it run cooler

leading to longer life.

• Solder joint reliability vastly improved.

- CTE of Copper (17 ppm/

C), matches the CTE of Typical

FR4 PWBs (15-17 ppm/

- CTE of Alloy 42 (5 ppm/

C), mismatch to CTE of FR4

PWBs (15-17 ppm/

• RoHS Version (NiPdAu plating)

- Most preferred for elimination of risk for whisker growth.

The use of copper lead frames inherently allow for better solder joint reliability, tin whisker prevention and

better thermal dissipation. These are three big factors in overall system reliability over time.

Better Solder Joint Reliability

Many systems are expected to operate reliably over broad temperature variations spanning the industrial

(-40

C to +85

C) and military (-55

C to +125

C) temperature ranges. System problems can be caused

by the mismatch of thermal coefﬁcients of all system components. Better solder joint reliability is obtained

since the copper lead frame is more

ﬂ

exible, and the CTE of the copper lead frame is better matched with

that of typical FR4 PWBs, than that of Alloy 42. Repeated thermal cycles over a period of time can take a

toll on solder joints, causing cracks and intermittent connections where expansion and contraction of the

lead frame is at a different rate than the FR4 PWB that it is attached to.

Whisker Prevention

The RoHS version of this copper lead frame, with its’ NiPdAu (Nickel-Palladium-Gold) plating, eliminates

the risk of tin whiskers. Microscopic whiskers can grow on a parts’ pins than have tin content in the plat-

ing. Traditionally Alloy 42 lead frames have a Sn or PbSn plating. This plating containing tin, along with

certain environmental conditions can cause these whiskers to grow. Their growth may extend to form a

bridge with another pin on the device, or the whisker may break off and cause a short circuit or even an

explosive power surge on the board. The organization, iNEMI (International Electronics Manufacturing

Initiative) lists the NiPdAu lead plating as the most preferred for elimination of risk for whiskers.

Better Thermal Dissipation

Because copper has a 10X to 12X improvement in thermal conductivity vs. Alloy 42, and since

ja and

characteristics of copper provide up to 3.8X advantage over Alloy 42, more efﬁcient thermal dissipation is

the result. This translates to better heat dissipated away from the chip through the lead frame and PWB,

thus extending the useful life of the die by reducing die junction temperature. Therefore less heat stress

remains in the device, which is a leading cause of non-mechanical failure in a long life application.

SDRAM

•

Source: ISSI white paper; “Enhancing Long-Term Reliability with Copper Lead Frames.”

AS4SD8M16

Rev. 1.1 04/10

Micross Components reserves the right to change products or speciﬁcations without notice.

AS4SD8M16DGC-75/IT Related Products

	AS4SD8M16DGC-75/IT	AS4SD8M16DGCR-75/ET	AS4SD8M16DGC-75/ET	AS4SD8M16DGC-75/XT	AS4SD8M16DGCR-75/XT	AS4SD8M16DGCR-75/IT
Description	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-54	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, PLASTIC, TSOP2-54	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-54	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PDSO54, 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-54
Maker	Micross	Micross	Micross	Micross	Micross	Micross
Parts packaging code	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
package instruction	TSOP2,	TSOP2,	TSOP2,	TSOP2,	TSOP2,	TSOP2,
Contacts	54	54	54	54	54	54
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	5.4 ns	5.4 ns	5.4 ns	5.4 ns	5.4 ns	5.4 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54	R-PDSO-G54
JESD-609 code	e0	e4	e0	e0	e4	e4
length	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm	22.22 mm
memory density	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	16	16	16	16	16	16
Number of functions	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1
Number of terminals	54	54	54	54	54	54
word count	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words
character code	8000000	8000000	8000000	8000000	8000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	85 °C	105 °C	105 °C	125 °C	125 °C	85 °C
Minimum operating temperature	-40 °C	-45 °C	-45 °C	-55 °C	-55 °C	-40 °C
organize	8MX16	8MX16	8MX16	8MX16	8MX16	8MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2	TSOP2
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES	YES	YES
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	MILITARY	MILITARY	INDUSTRIAL
Terminal surface	TIN LEAD	NICKEL PALLADIUM GOLD	TIN LEAD	TIN LEAD	NICKEL PALLADIUM GOLD	NICKEL PALLADIUM GOLD
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
width	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.16 mm

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