the chip into an ultra low power mode, with data preserved.
74,24
Bidirectional I/O Parity lines. As inputs they reach the memory
array via an input register, the address stored in the register on the
rising edge of clock. As and output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delieverd is from the previous clock period of the READ cycle.
58, 59, 62, 63, 68, 69,
Bidirectional I/O Data lines. As inputs they reach the memory
72, 73, 8, 9, 12, 13, 18,
array via an input register, the address stored in the register on the
19, 22, 23
rising edge of clock. As and output, the line delivers the valid data
stored in the array via an output register and output driver. The data
delieverd is from the previous clock period of the READ cycle.
31
Interleaved or Linear Burst mode control
91, 15, 41, 65
Core Power Supply
90, 17, 40, 67
Core Power Supply Ground
4, 11, 20, 27, 54, 61,
Isolated Input/Output Buffer Supply
70, 77
5, 10, 21, 26, 55, 60,
Isolated Input/Output Buffer Ground
71, 76
1, 2, 3, 6, 7, 14, 16, 25,
No connections to internal silicon
28, 29, 30, 38, 39,
51, 52, 53, 56, 57, 66,
75, 78, 79, 95, 96
Micross Components reserves the right to change products or specifications without notice.
Chip Enable
Chip Enable
Global Write Enable
Byte Enables
Byte Write Enable
Output Enable
Address Strobe Controller
CE1\, CE3\
CE2
GW\
BWa\, BWb\
BWE\
OE\
ADSC\
Input
Input
Input
Input
Input
Input
Input
87
86
85
Address Strobe from Processor
ADSP\
Input
Address Advance
Power-Down
Data Parity Input/Outputs
ADV\
ZZ
DQPa, DQPb
Input
Input
Input/
Output
Data Input/Outputs
DQa, DQb, DQc
DQd
Input/
Output
Burst Mode
Power Supply [Core]
Ground [Core]
Power Supply I/O
I/O Ground
No Connection(s)
MODE
VDD
VSS
VDDQ
VSSQ
NC
Input
Supply
Supply
Supply
Supply
NA
AS5SP1M18
Rev. 1.9 09/11
2
SSRAM
AS5SP1M18
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (t
CO
) is 3.0 ns (200
MHz device). The AS5SP1M18 supports secondary cache
in systems using a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486
TM
processors.
The linear burst sequence suits processors that use a linear
burst sequence. The burst order is user selectable, and is
determined by sampling the MODE input. Accesses can be
initiated with either the processor address strobe (ADSP\) or
the controller address strobe (ADSC\). Address advancement
through the burst sequence is controlled by the ADV\ input.
A two-bit on-chip wraparound burst counter captures the first
address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the byte write enable
(BWE\) and byte write select (BW\
X
) inputs. A global write
enable (GW\) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous chip selects (CE\
1
, CE\
2
, CE\
3
) and an
asynchronous output enable (OE\) provide for easy bank
selection and output tri-state control. ADSP\ is ignored if CE\
1
is HIGH.
Single Write Accesses Initiated by ADSP\
This access is initiated when both the following conditions are
satisfied at clock rise: (1) ADSP\ is asserted LOW and (2) CE\
1
,
CE\
2
, and CE\
3
are all asserted active. The address presented
to A is loaded into the address register and the address
advancement logic while being delivered to the memory array.
The write signals (GW\, BWE\, and BW\
X
) and ADV\ inputs are
ignored during this first cycle.
ADSP\ triggered write accesses require two clock cycles to
complete. If GW\ is asserted LOW on the second clock
rise, the data presented to the DQs inputs is written into the
corresponding address location in the memory array. If GW\
is HIGH, then the write operation is controlled by BWE\ and
BW\
X
signals.
The AS5SP1M18 provides byte write capability that is described
in the write cycle descriptions table. Asserting the byte write
enable input (BWE\) with the selected byte write (BW\
X
) input,
selectively writes to only the desired bytes. Bytes not selected
during a byte write operation remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations.
The AS5SP1M18 is a common I/O device, the output enable
(OE\) must be deserted HIGH before presenting data to the
DQs inputs. Doing so tri-states the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a write
cycle is detected, regardless of the state of OE\.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP\ or ADSC\ is asserted LOW,
(2) CE\
1
, CE\
2
, CE\
3
are all asserted active, and (3) the write
signals (GW\, BWE\) are all deserted HIGH. ADSP is ignored if
CE\
1
is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the address
register while being presented to the memory array. The
corresponding data is enabled to propagate to the input of the
output registers. At the rising edge of the next clock, the data is
enabled to propagate through the output register and onto the
data bus within 3.0 ns (200 MHz device) if OE\ is active LOW.
The only exception occurs when the SRAM is emerging from
a deselected state to a selected state; its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE\ signal.
Consecutive single read cycles are supported. Once the SRAM
is deselected at clock rise by the chip select and either ADSP\
or ADSC\ signals, its output tri-states immediately.
Single Write Accesses Initiated by ADSC\
ADSC\ write accesses are initiated when the following conditions
are satisfied: (1) ADSC\ is asserted LOW, (2) ADSP\ is deserted
HIGH, (3) CE\
1
, CE\
2
, and CE\
3
are all asserted active, and
(4) the appropriate combination of the write inputs (GW, BWE,
and BW\
X
) are asserted active to conduct a write to the desired
byte(s). ADSC\-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV\ input is ignored during
this cycle. If a global write is conducted, the data presented to
the DQs is written into the corresponding address location in
the memory core. If a byte write is conducted, only the selected
bytes are written. Bytes not selected during a byte write operation
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
The AS5SP1M18 is a common I/O device, the output enable
(OE\) must be deserted HIGH before presenting data to the
DQs inputs. Doing so tri-states the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a write
cycle is detected, regardless of the state of OE\.
AS5SP1M18
Rev. 1.9 09/11
Micross Components reserves the right to change products or specifications without notice.
3
SSRAM
AS5SP1M18
Burst Sequences
The AS5SP1M18 provides a two-bit wraparound counter,
fed by A1: A0, that implements an interleaved or a linear
burst sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input. Asserting ADV\ LOW at clock rise
automatically increments the burst counter to the next address
in the burst sequence. Both read and write burst operations
are supported.
Interleaved Burst Address Table
(MODE=Floating or VDD)
First
Address
A1:A0
00
01
10
11
Second
Address
A1:A0
01
00
11
10
Third
Address
A1:A0
10
11
00
01
Fourth
Address
A1:A0
11
10
01
00
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation sleep mode. Two clock cycles
are required to enter into or exit from this sleep mode. While
in this mode, data integrity is guaranteed. Accesses pending
when entering the sleep mode are not considered valid nor is
the completion of the operation guaranteed. The device must
be deselected prior to entering the sleep mode. CE\
1
, CE\
2
,
CE\
3
, ADSP\, and ADSC\ must remain inactive for the duration
of t
ZZREC
after the ZZ input returns LOW.
Linear Burst Address Table (MODE=GND)
First
Address
A1:A0
00
01
10
11
Second
Address
A1:A0
01
10
11
00
Third
Address
A1:A0
10
11
00
01
Fourth
Address
A1:A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter Description
I
DDZZ
Sleep mode standby current
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
ZZ VDD – 0.2V
ZZ VDD – 0.2V
ZZ 0.2V
This parameter is sampled
This parameter is sampled
Min
Max
150
2t
CYC
Unit
mA
ns
ns
ns
ns
2t
CYC
2t
CYC
0
AS5SP1M18
Rev. 1.9 09/11
Micross Components reserves the right to change products or specifications without notice.
4
SSRAM
AS5SP1M18
TRUTH TABLE
4,5,6,7,8
Operation
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Sleep Mode, Power Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Add. Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CE\
1
H
L
L
L
L
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CE\
2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
CE\
3
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP\
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
ADSC\
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV\ WRITE\
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
H
X
H
L
H
L
H
L
H
L
H
L
L
L
L
H
H
H
H
H
H
H
H
H
L
H
L
OE\
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
CLK
LH
LH
LH
LH
LH
X
LH
LH
LH
LH
LH
LH
LH
LH
LH
LH
LH
LH
LH
LH
LH
LH
LH
DQ
Tri State
Tri State
Tri State
Tri State
Tri State
Tri State
Q
Tri State
D
Q
Tri State
Q
Tri State
Q
Tri State
D
D
Q
Tri State
Q
Tri State
D
D
Notes
4. X = Don’t Care, H = Logic HIGH, L = Logic LOW.
5. WRITE\ = L when any one or more byte write enable signals, and BWE\ = L or GW\ = L. WRITE\ = H when all byte write enable signals, BWE\, GW\ = H.
6. The DQ pins are controlled by the current cycle and the OE\ signal. OE\ is asynchronous and is not sampled with the clock.
7. The SRAM always initiates a read cycle when ADSP\ is asserted, regardless of the state of GW\, BWE\, or BW\
X
. Writes may occur only on subsequent clocks
after the ADSP\ or with the assertion of ADSC\. As a result, OE\ must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE\ is a
don’t care for the remainder of the write cycle.
8. OE\ is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE\ is
inactive or when the device is deselected, and all data bits behave as output when OE\ is active (LOW).
TRUTH TABLE FOR READ/WRITE
4,9
Function
Read
Read
Write Byte A – (DQ
A
and DQP
A
)
Write Byte B – (DQ
B
and DQP
B
)
Write Bytes B, A
Write All Bytes
Write All Bytes
GW\
H
H
H
H
H
H
L
BWE\
H
L
L
L
L
L
X
BW\
B
X
H
H
L
L
L
X
BW\
A
X
H
L
H
L
L
X
Note
9. Table only lists a partial listing of the byte write combinations. Any combination of BW\
X
is valid. Appropriate write is done based on which byte write is active.
AS5SP1M18
Rev. 1.9 09/11
Micross Components reserves the right to change products or specifications without notice.
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